Who will do ATPG in Asic design team ?

[DeepIC]

ATPG

In asic design team, who will responsible for ATPG? Front-end designer
or back-end designer?

 

[jazz_roa]

The front-end designers are responsible for ATPG, they know how to make their design meet the DFT requirements. By the way, some back-end tools do fix some (hold-time) timing violations or modify the scan chain for routibility.

 

[eternal_nan]

In big companies, generally there is
a separate DFT group which is in charge
of inserting DFT related logic and
generating scan patterns (using either
ATPG or dumping functional patterns).

In small companies, I have seen both
back end and front end people do it. It
is a easy task, most of the time. It just
depends on who's got more free time

 

[kermit]

can you give me some suggestion about ATPG?

Pls tell me what tools to produce the atpg test vector?

 

[jobnom99]

atpg pattern

there are some tools for atpg.

but, alomost pepple use as bellows tool.

1. synopsys test_compiler ( until 2001.08 version)
Synopysys testgen
Synopsys TetraMax ( now )

2. Syntest

3. veritest

4. mentor DFT architecture

 

[sandusty]

ATPG

PM, Product Manager, is responsible!!
He (PM) assigned anyone he want to do the job..

 

[rod_wu]

Re: ATPG

Who knows where can get "Synopsys TetraMax" software?

Thanks

 

[davorin]

Re: ATPG

1. Off-topic!!!

2. Ask Synopsys about your local sales office...

 

[wang1]

Re: atpg pattern

there are some tools for atpg.

but, alomost pepple use as bellows tool.

1. synopsys test_compiler ( until 2001.08 version)
Synopysys testgen
Synopsys TetraMax ( now )

2. Syntest

3. veritest

4. mentor DFT architecture

The ATPG tool of Ment0r should be F@stscan for full or almost full scan,
f/l/extest for patitial scan.

 

[gerade]

Re: ATPG

DFT issue should be cover throughout the entire flow
1.testing guy will have a test concept at the begining
2.then this is planed by FE guy(usually a specify person will be reponsible for this)
3.implement this concept in the design
4.after all the RTL finish, run through scan chain insertion and ATPG coverage, feed back the weak point to the RTL designers to improve the coverage.

so far this is what i know, and I am sure that for the BE they also will have some consideration of ATPG from the beginning

 

[amjad]

ATPG

Cadence testbench is another ATPG tool

 

[troops]

ATPG

synopsys : tetramax
mentor graphic : DFT
these are powerful .....

 

[ken_ooi]

Re: ATPG

Its depends on the ASIC design methodology and flows implement by the company.
It can be:
- Specific DFT group responsible for test circuit insertion & ATPG.
- FE designer reponsible for test circuit insertion, DFT design rule check and test coverage, and Test engineer reponsible for full ATPG.

 

[visualart]

ATPG

I think that the ATPG must independ on any other partts, It must do by the experience engineer.

 

[melonpy]

Re: ATPG

ATPG pattern can be given after chip tapeout and befor mass pro. It's a relative independent step.
But scan insertion, bist and boundary scan must be considered from start of project.

 

[zzy_zy]

ATPG

Do Synopsys TetraMax can be used under windowsXP?

 

[elektor]

Re: ATPG

No .
Only Unix/Linux machine.

Regards

Elektor

 

[pamulurureddy]

ATPG

Now a days there are seperate team for the DFT and they will take care of that

 

[haosg]

Re: ATPG

of course , the FE are responsibel for ATPG,
but the netlist should be after apr.

 

[pamulurureddy]

Re: ATPG

Yes i am agreeing with you. front end engineer only responsible but from my project we are not doing any thing with DFT.