Who will do ATPG in Asic design team ?

[floatgrass]

Re: ATPG

now , physical synthesis designer do dft in many companys.

 

[maxsnail]

Re: ATPG

ATPG doest care timing, so it can start working when scan chain is stiched.
primetime and dynamic simulation to check timing

 

[kctang]

Re: ATPG

My opinion is FE design should bare DFT in their mind during design.

It's because a design with DFT violation needs huge effort to fix it for ATPG especially the FE designer don't want to modify their freezed design(I'm a FE designer but seeing so many colleagues have DFT ignorance behavior).

 

[sarath51]

Re: ATPG

Cadense Test Enconuter also gives an effective way for DFT and ATPG

 

[fengjin]

Re: ATPG

in my opinion, FE should be responsible for ATPG ,just because BE is not familiar with the system designed

 

[tybhsl]

Re: ATPG

hi
what's ATPG ? Thanks.

 

[joe2moon]

Re: ATPG

ATPG stands for "Automatic Test Pattern Generation".
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As long as the scan circuit(s) have been inserted into the design and scan mode timing is met,
then in my humble opinion,
any one who knows to use the ATPG tool(s), such TetraMax, FastScan, or Encounter Test,
can do this job.

 

[wkong_zhu]

ATPG

ATPG is not so easy, I think.
Because I am doing it now.

I share TEST_EN TEST_CLK TEST_MODE with functional IO pins.

 

[zzy_zy]

ATPG

Is ATPG an important job in the asic design?

 

[kctang]

Re: ATPG

To wkong_zhu:
You're so unlucky that your test mode pins has to be shared with normal I/O. I know the pain on defining the init. test protocol in this situation...
My suggestion is to use dedicated I/O for these test pins...

To zzy_zy:
ATPG is very important. You can think of a 16bit adder as an example. If you want to do exhausive test on this adder, you'll need 2^(32) patterns to test this adder. ATPG
(with scan & BIST) virtually flattens your design during production test by apply & capture internal signals through scan flops. So your test pattern will be much smaller.