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who can tell me "what is Transition " ?

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nine8

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what is "Transition" in Asic ?
:D

什么是tansition ?嘿嘿,不知道有没有装中文的
 

rising or falling time at o/p of a standered cell is called as Transition

i.e, load takes some time to charge or discharge right

i hope it will help you
 

Whenevera signal chages its value from '0' to '1' or '1' to '0' we call it as transition.
 

nine8 said:
what is "Transition" in Asic ?
:D

什么是tansition ?嘿嘿,不知道有没有装中文的

yup, when output signal changes, it goes a gradual rise/fall in analog domain..

如果没有读懂英文的话,芯片设计的软件很难用哟。:!:
 

Thank you , to:
Amruth , vikas_lakhanpal27, kelvin_sg

But i want to know if it must be considered,when doing synthesis with DC ? if does , By which factor is the "transiton" set ?

+++++++++++++++++++++++++++++
E文不怎么好,大家别笑我哈,中国人真多啊,呵呵,上回在论坛上还看到个用周星驰头像的朋友,挺搞笑的
 

u r transition in the synthesis level is depends on the wire load models . i hope u know wat is wire load model.

wire load model is a timing model it depends upon the fanout
 

Transition should be set based on the library being used
 

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