cnz said:who can help me?
Can you tell me how to design a kind of memory such as sdram or dram?
tlihu said:Check out this site
there are some tutorials on memory design.
Could you please share me the two books?sunjimmy said:Hi,
Actually memory is pure analog(or transistor) level design. The delay parameters you saw in Verilog model comes from Spice simulation with actual circuit netlist plus some parasitic RC elements. So it doesn't make any sense to add any delay by yourself to any verilog memory model provided from IP vendors/foundary. If you are interesting about memory design, you may refer to the following books for your reference : )
1. CMOS Memory Circuits
By Tegze P. Haraszti
Kluwer Academic Publisher 2000
2. VLSI Memory Chip Design
By Kiyoo Itoh
Hope it helps : )