Who can tell me how to design memory?

[cnz]

who can help me?

Can you tell me how to design a kind of memory such as sdram or dram?

thanks!

 

[snaityma]

who can help me?

Can you tell me how to design a kind of memory such as sdram or dram?

thanks!

It's not easy topics
In my opinions, you should read some documents and books, first.

 

[tlihu]

Check out this site

h**p://cmosedu.com/jbaker/courses/ee5497/

there are some tutorials on memory design.

Good luck.

 

[cnz]

thanks a lot!

I want know if some foundry vendors can offer memory micracell and
how to simulate the memory?


ps: I only want to know how to design the ROM and RAM for 8051!

thanks again!

 

[jk]

for sure - many foundries have memory-generators, but normally they just propose you to generate a macrocell on demand. In most cases you can generate a VHDL- or Verilog-Model of the memory, that you can use for simulation. Some propose some tools to get a first impression of area, power consumption, etc.

 

[cnz]

however,how to add true delay to this vhdl (or verilog)memeory model?

 

[mutoucanada]

please go to www.opencores.org.

 

[cnz]

where?

 

[icnewer]

No access to this website now!

Check out this site

h**p://cmosedu.com/jbaker/courses/ee5497/

there are some tutorials on memory design.

Good luck.

can't access to the websit. who can tell how to access?
I also want to learn how to design MEM.

 

[sunjimmy]

Hi,

Actually memory is pure analog(or transistor) level design. The delay parameters you saw in Verilog model comes from Spice simulation with actual circuit netlist plus some parasitic RC elements. So it doesn't make any sense to add any delay by yourself to any verilog memory model provided from IP vendors/foundary. If you are interesting about memory design, you may refer to the following books for your reference : )

1. CMOS Memory Circuits
By Tegze P. Haraszti
Kluwer Academic Publisher 2000

2. VLSI Memory Chip Design
By Kiyoo Itoh
Springer 2001

Hope it helps : )

 

[cyrabbit]

Hi,

Actually memory is pure analog(or transistor) level design. The delay parameters you saw in Verilog model comes from Spice simulation with actual circuit netlist plus some parasitic RC elements. So it doesn't make any sense to add any delay by yourself to any verilog memory model provided from IP vendors/foundary. If you are interesting about memory design, you may refer to the following books for your reference : )

1. CMOS Memory Circuits
By Tegze P. Haraszti
Kluwer Academic Publisher 2000

2. VLSI Memory Chip Design
By Kiyoo Itoh
Springer 2001

Hope it helps : )

Could you please share me the two books?