synopsys
Program can gain early access to Synopsys' SystemVerilog-based tools, such as VCS™ and HDL Compiler, the front-end language compiler for Design Compiler™, for development and support of their respective SystemVerilog tools, IP and training products. By participating in the SystemVerilog Catalyst Program, member companies can help provide their customers with a more effective path to interoperability with Synopsys' SystemVerilog-based tools and Accellera SystemVerilog language.