Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
synopsys
Program can gain early access to Synopsys' SystemVerilog-based tools, such as VCS™ and HDL Compiler, the front-end language compiler for Design Compiler™, for development and support of their respective SystemVerilog tools, IP and training products. By participating in the SystemVerilog Catalyst Program, member companies can help provide their customers with a more effective path to interoperability with Synopsys' SystemVerilog-based tools and Accellera SystemVerilog language.
I think all the three major vendors (SNPS, MENT, CDN) have some support. AFAIK, SNPS leads it, followed by MENT (Questasim) then Cadence - but things are changing as we speak. Check with your vendor.
I think all the three major vendors (SNPS, MENT, CDN) have some support. AFAIK, SNPS leads it, followed by MENT (Questasim) then Cadence - but things are changing as we speak. Check with your vendor.
All,
It will surely help all of us - the tech community, to quantify when we say "way ahead of xyz". Is there a list of constructs/context which one supports better than others? For example:
Interface + Modport + Clocking block support.
Program, Multiple programs
VMM kind of heavy OOP based code.
I would not get into who is better as I've NDA with more than one vendor, but for us to say "one is ahead of other" we would need a quantification IMHO.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
