X1, X2 etc. are drive strengths if following the standard convention that we usually use.
Which one is faster is difficult to answer from that pic. Higher X means higher input cap, but on resistance is smaller. Lower X is opposite. But I'd say the 2nd is most probably faster to charge/discharge the capacitor.
Lets make an assumption: the delay for each stage be RC where C is only the load.
For the first circuit: delay1 = Rinv*Cinv + Rinv*C
For second circuit: delay2 = Rinv*2.5*Cinv + (Rinv/2.5)*C
If you equate the two delays it will give a critical value of C which is 2.5*Cinv.
Hence delay for ckt 1 is smaller for C < 2.5 Cinv and larger for C > 2.5*Cinv. Both circuits will have equal delay for C = 2.5*Cinv
Delay of any stage is the product of the resistance of the device and the sum of self and load capacitance. Generally the PMOS and NMOS of an inverter are sized to have equal resistance. Hence rising and falling delays are equal.
Circuit 1:
stage I: resistance = Rinv; capacitance = drain capacitance of first inverter + gate capacitance of second inverter. Assume Cgate = Cdrain. Then,
delay1_stage1 = Rinv*2*Cgate (since Cgate + Cdrain = 2*Cgate)
stage II: resistance = Rinv; capacitance = Cgate + C (here C is the load shown in the problem statement)
delay1_stage2 = Rinv*(Cgate + C)
Total delay of circuit1 = delay1_stage1 + delay2_stage2 = Rinv(3*Cgate + C)