Which layout is better?

[tony_lth]

I have two RF trace, one is TX trace, and the other is RX trace. For the layout, I have two options:
1st: the two traces are on the same layer.
2nd: the two traces are on the two different lays.
I have two questions:
1. Which one is better?
2. How to simulate it?

 

[thylacine1975]

Hiya Tony, you're after the strategy that maximises the isolation attained between the two traces.

I've found the main culprit (of unwanted couplings) on a PCB is excitation of a 'parallel plate' TEM waveguide mode between the ground/power plane and the signal plane/layer. If you're using coplanar waveguide (with ground - i.e. CPWG) structures and you're stuck with the Tx/Rx traces on the same layer, placing closely spaced vias bridging the two grounded regions (layers) in between the signal lines will greatly suppress undesired coupling (by inhibiting TEM propagation).

If you can place the signal lines on different layers though - with a ground plane in between them - this is definitely preferable.
If a plane between the layers is not possible, then the traces on the same routing layer (with a plane underneath) would be preferred.

I presume the Tx and Rx traces are of a controlled impedance, i.e. microstrip/CPWG or similar? (If they're not, then their relative isolation is anyone's guess!

As a guideline, I've (empirically) found that for two parallel microstrip lines of ~a wavelength long on the same PCB layer, the coupling between each is < -40 dB by the time they're 10x the dielectric spacing apart. (Thinner dielectrics are better from a radiation loss/coupling perspective too btw.) There's so many variables though - the only way I know to simulate/check for sure would be an EM solver (e.g. ADS, Sonnet, HFSS, CST etc) although perhaps someone knows of an easier (cheaper) alternative?

Cheers

 

[tony_lth]

Hi, thylacine1975, thanks for your comments.
Yes, the both traces are controlled impedance and in CPWG structures.
How about the following two options? Which is better? (L1 denotes Layer 1, G denotes GND, Cut denotes cut out, T denotes trace on this layer.)
Option1: (i.e. TX and RX on the same layer)
TX: L1(G), L2(Cut), L3(Trace), L4(Cut), L5(G)
RX: L1(G), L2(G), L3(Trace), L4(Cut), L5(G)
Option2: (i.e. TX and RX on the adjacent two layers)
TX: L1(G), L2(Cut), L3(Trace), L4(Cut), L5(G), L6(G)
RX: L1(G), L2(G), L3(G), L4(Trace), L5(Cut), L6(G)

 

[tony_lth]

I know HFSS can simulate it, but how to setup the ports? obviously waveport is not fitful.

 

[thylacine1975]

Hiya Tony!
(Apologies for the tardy response, I'm on holidays..! [and logged in via my smartphone for some daft reason ])

The neat sketch I did of (my interpretation) of your two options is unhelpfully laying next to the keyboard in my office, but it wasn't obvious to me which of them was better, in the absence of vias shorting the ground planes together. Clearly the best option would be to have the TX and RX traces on opposite sides of a ground plane if at all possible. If that can't be done, then liberal vias pinning the various ground planes together between (and around) the signal traces is probably as good as can be achieved.
Unfortunately I'm not at all familiar with HFSS, but in CST you could use either the discrete or waveguide ports successfully for this problem. To use the waveguide port, let the port extend from the lowest ground plane to ~one dielectric thickness above the PCB in the vertical dimension, and make the horizontal extent ~6 dielectric thicknesses, with the signal trace in the centre to adequately represent all of the relevant modes.

If my rambling would be improved with a sketch, let me know and I'll draw one up next week!
Good luck

 

[tony_lth]

Hi, thylacine1975,
Thanks for your reply.
The GND vias are 75um in diameter and the two traces are surroundings with them. The vias are seperated in 300um.
The trace is 60um width (50 ohms impedance), and the freq is 2GHz.
Every layer is 70um height, with trace thickness 20um, and the Er is 4. (FR4 substrate).
I will try to simulate it in HFSS.

 

[tony_lth]

Hi, according to my coarse simulation results,

option1 is better than option 2.