[SOLVED] Why there is a difference in the ADS layout and schematic simulation results?

[Nathan1]

I am working on a rectifier. There is a difference in the layout and schematic simulated result (S11 plot attached). I know that the layout result usually differs from the schematic. Is it normal to have this much of a difference in the S11 plot as in the screenshot attached? The layout simulation result can be improved, but I'll do it once it's confirmed by someone that my EM setup is correct (ports settings, etc).

I have used TML for the input port as mentioned by volker@muehlhaus in his posts. Also used TML for the output port.

Dimensions of the Tlines and stubs are the same in schematic and layout. I have attached the layout, substrate (for both layout and schematic) and ports screenshot. Please have a look.

Thanks a lot.

 

[volker@muehlhaus]

You have very different widths in TEE-junctions and large steps in width. Circuit models are not very accurate for these extreme dimensions. In this case, EM can be more accurate.

 

[Nathan1]

You have very different widths in TEE-junctions and large steps in width. Circuit models are not very accurate for these extreme dimensions. In this case, EM can be more accurate.

Thanks a lot, volker@muehlhaus. EM setup (ports setting) etc I have shared are fine, I guess?

 

[volker@muehlhaus]

EM setup (ports setting) etc I have shared are fine, I guess?

This is difficult to answer from the incomplete screenshots that you showed. You have placed some ports (P3, P12) and ground symbols near the vias that look strange to me.

 

[Nathan1]

This is difficult to answer from the incomplete screenshots that you showed. You have placed some ports (P3, P12) and ground symbols near the vias that look strange to me.

Thanks a lot, volker@muehlhaus. There was an extra gnd symbol I removed. The attached screenshot shows how I got gnd symbol. To further assess whether my setup is appropriate, I would like to share anything else you may need to know? I really appreciate your help.

 

[volker@muehlhaus]

I think this looks OK now.

 

[Nathan1]

I think this looks OK now.

Thank you very much.

 

[BigBoss]

Use VIA from palette in schematic view.. Do not place manually VIAs over copper pour.

 

[Nathan1]

Thanks a lot, @BigBoss. I used ViaGnd it seems better. As shown in the screenshots above, do I still need to ground the short stub manually? In the schematic, we can't connect via to a short stub.

 

[BigBoss]

It's easy to connect a VIA to a component. Check the connections physically.
Simulation results should be very close. 

 

[volker@muehlhaus]

As shown in the screenshots above, do I still need to ground the short stub manually?

Placing the ground symbol has an effect for schematic simulation, but it has zero effect for layouts simulated in EM. The EM solution is based only on physical elements drawn in layout.

This means the ground symbol placed in layout at P13 etc is useless and misleading. Current in the EM model will flow through the two physical vias that you have drawn there.

 

[Nathan1]

It's easy to connect a VIA to a component. Check the connections physically.
Simulation results should be very close. View attachment 184468

View attachment 184467

View attachment 184464

Thank you @BigBoss . I will replace the shorted stub with a microstrip transmission line and a VIAGND..

 

[BigBoss]

Thank you @BigBoss . I will replace the shorted stub with a microstrip transmission line and a VIAGND..

Yeah, that's it. You don't have to use shorted stub.

 

[Nathan1]

Yeah, that's it. You don't have to use shorted stub.
View attachment 184483
View attachment 184484
View attachment 184485

Thank you very much.

 

[volker@muehlhaus]

Yeah, that's it. You don't have to use shorted stub.

I don't like this approach. As you can see, the notches in S21 are off by more than 10%. This is due to the incorrect modelling of length at the shorted end when placing vias into the line.

 

[BigBoss]

I don't like this approach. As you can see, the notches in S21 are off by more than 10%. This is due to the incorrect modelling of length at the shorted end when placing vias into the line.

VIAs are not placed into the Line, they are attached to the Line. They seem to be but not true.
You're somehow right because VIAs' copper pours extend the TL's length.

If I place an alongside thin VIA at the end of the TL, the difference is very minor.

 

[Nathan1]

VIAs are not placed into the Line, they are attached to the Line. They seem to be but not true.
You're somehow right because VIAs' copper pours extend the TL's length.
View attachment 184500
If I place an alongside thin VIA at the end of the TL, the difference is very minor.
View attachment 184501
View attachment 184502

Yeah. In my case, after adding VIA, I had good results after adjusting the stub length. Thanks @volker@muehlhaus and @BigBoss.