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Which is better bus style tri-state or mux ?

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Specifically for Xilinx' FPGAs, I think that the tri-state mux approach is
better since there are plenty of tristate gates on the chip, meant exatly to
be used for this purpose, so you are left over with more general resources
(CLBs) to do other stuff.
 

rx300 said:
Our ASIC design practice is: inside the chip, MUX only. No tri-state.
External bus, tri-state if necessary.

Tri-state has problems such as timing and power consumption, as posted by another fellow. Avoid tri-state if you're doing ASIC design.

FPGA is different. FPGA devices have tri-state buffers built in. In some cases, it makes sense to use those tri-state buffers to drive long lines that are shared by blocks. This trick reduces routing congestions. However, tri-state buffers are slow, be aware of it.

I agree with this, this is what most of them use
 

Is Xilinx CPLD 9536XL suitable for tri-state bus?
 

cdcll said:
Is Xilinx CPLD 9536XL suitable for tri-state bus?

I don't think the Xilinx 9536XL supports internal tristate. If you aretalking external tristate then yes.
 

bus style

Mux is better in small design, and tristate is better of large design.
The timing for mux is bad when the design is large, so we should tri.
 

When you design PCB, you'd better choose TRI-STATE....
When you design ASIC, you's better choose MUX....

MUX is smaller than TRI-STATE......
so speed is faster....
 

and...

and if you have a error on a tristate bus, for example two driver, you can burn you chip!
So be carefully with tristate busses. And if you use Altera, the best way is to use multiplexed busses!!

Phytex
 

mux

I have designed several SOC chips and made that mistake only first time. If you want your design to work and you to sleep, stay away from tri-sate buses on the silicon. Even on boards they are troublemakers.

Zvrle
 

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