What will the D flip flop read from this state ?

[Xenon02]

Hello !

I've been watching a video about how UART was made from scratch, but I've encountered one problem I couldn't answear.

The author of a video :

, has used the counter : 74LS165. There was one problem. Because the SHIFT/LOAD bit was changed at the same time as CLK. What do I mean is that the SHIFT/LOAD changed from 0 -> 1 at the same time the clock CLK changed from the 0 -> 1 like in the picture :

What will the D flip flop do ?
Will it still be using asynchronous inputs or shift with synchronous input ?
Because both Load/Shift and CLK are the rising bits.
And D flip flop reads during the rising CLK like here :

But in this situation :

Both of them are rising, it is not simple logic level like in the picture with D and CLK (in which D has a certain level).

In author circuit it worked, but I didn't know why when I see SH/LD is a rising bit synchronized with CLK rising bit.

 

[FvM]

Review 74165 datasheet. It has timing conditions (e.g. setup delay between SH/LD and CLK) that must be met for correct operation. If setup requirements are violated, logic output isn't predictable.

 

[Xenon02]

Review 74165 datasheet. It has timing conditions (e.g. setup delay between SH/LD and CLK) that must be met for correct operation. If setup requirements are violated, logic output isn't predictable.

I have checked the datasheet, but I didn't really much understood it, and tried to compare it to the picture of what author got.

Because this purple/pink signal is both for clock and for the SH/LD so they at the same time rise and fall. I believe what I said has any sense here ;D Because this yellow signal is also for the clock but this pink/purple signal is also part of the clock.

Theoretically as I know this is a logic hazard ? Because both Clock and Signal are rising at the same time so it doesn't know whether it is "1" or "0" in the input. For the D flip flop here the Clock that sets the D flip flop at least I don't know if it's "0" for synchronic reading from "D" input or Asynchronic which is set/reset inputs. What I'm trying to say is that the rising signal doesn't tell me if it's still 0 or 1 thus when CLK is rising what D flip flop will interpret, the asynchronic or synchronic ? I don't know how to explain it

I also know they are not ideal elements and the inputs have delays. But I don't know how to interpret it to this example and both SH/LD and CLK have the same timing. But in author circuit it interprets it always as LD and not as SH even though both SH/LD and CLK are rising which is weird for me and I don't understand it.

 

[D.A.(Tony)Stewart]

Back in 1976 I designed a UART with small scale logic using the setup and hold times to make it work. You just need to follow the timing for prop delay, setup and hold times to make it work when signals are synchronous.

 

[Xenon02]

Back in 1976 I designed a UART with small scale logic using the setup and hold times to make it work. You just need to follow the timing for prop delay, setup and hold times to make it work when signals are synchronous.

Hello !

That's why I've asked why it worked in that case. How should I interpret that SH/LD and CLK have the same rising moment because they are both synchronized. I read something in the datasheet that I didn't much understand and tried to come up with the explanation, why it worked in that case (good to notify the CLK_INH in this case is always 0, author grounded this pin). So this SH/LD and CLK rising at the same time is confusing and I can't explain why it worked thus can't imagine what it interprets it as "0" or "1". It's hard to explain.

I see from the post that it's about delays but I don't see them in the video because the same rise is passed to both inputs at the same time, so the delays are the same I guess ? So D flip flop doesn't know if it's "0" or "1" so it's a hazard ? But it happened to be always "0" in this type of situation which I don't understand looking at video osciloscope and knowing that both CLK and SH/LD get the same bit from the same output which is shown in the osciloscope (or maybe they get from different output but on the osciloscope it matches).

I don't get it ...

Looking at this also confuses me because like I said both of them raises, and maybe they are delayed but I don't see it exactly (on the osciloscope of the video) and how it was achieved and how he was sure (it wasn't explained how it worked for him the author just plugged it ).
And it a bits breaks my logical thinking here because I always interpreted these type of situations as logic hazard ? Or something that give unpredictible output.

Usually in tutorials about D flip flop they don't show the situations when CLK and D are both rising at the same time, and here the SH/LD and CLK are the same type of situation.

PS.

Yes the purple/pink is imposes a yellow signal in the osciloscope (yellow is the CLK, purple is passed to SH/LD) so the yellow is not visible under purple/pink because they are I think identical ? If so where there is delay that makes both rising signals work and makes even if SH/LD is rising the D flipflop will read SH/LD as 0 and not as 0/1 because its rising.

I don't get it ...

 

[FvM]

I would expect that CLK edge is ignored if it's coinciding with SH rising edge (SH = 1 setup time of zero). But this side of nLD/SH to CLK relation isn't exactly specified. In any case there's a range where DFF output isn't predictable.

Please notice that nLD/SH is driving asynchronous DFF inputs. Don't confuse the problem with synchronous D to CLK setup/hold time. D has negative hold time in usual DFF, that's why synchronous logic works.

 

[Xenon02]

I would expect that CLK edge is ignored if it's coinciding with SH rising edge (SH = 1 setup time of zero). But this side of nLD/SH to CLK relation isn't exactly specified. In any case there's a range where DFF output isn't predictable.

Why thought did you expected that CLK would be ignored ?
LD/SH are a bit specified that it's good to use CLK_INH to load value (which I understood and was logical), but the author didn't use the CLK_INH which lead me to the point of "how did he know that CLK will "lock" the SH/LD rising edge and identify it as "0" always and not "1").
Random luck that it worked ?

In any case there's a range where DFF output isn't predictable.

That's why I thought this is one of the unpredictable behaviors but it somehow was always interpreted the rising SH/LD as 0 always.

Please notice that nLD/SH is driving asynchronous DFF inputs. Don't confuse the problem with synchronous D to CLK setup/hold time.

Exactly ! I've noticed it but, it depends on the SH/LD whether the D Flip Flop works as asynchronous or synchronous, and if SH/LD is equal 1 then D Flip Flop is synchronous and if SH/LD is equal 0 then D Flip Flop is Asynchronous.

So when SH/LD = 1 then CLK is ignored, if SH/LD = 0 then CLK matters and loads the D input into D - Flip Flop, but there is a situation that SH/LD is not equal 1 nor 0 it's rising.

So when I don't know what is SH/LD then I don't know what CLK will do at rising clock, it can either be ignored or do something but this rising SH/LD is at the same time confusing and misleading. I would do something to prevent from these type of situations.

It still confused me and doesn't answer fully my question of "why" it worked in the author size, how he know it will always work like that and why it wasn't in the datasheet ? The logic I was taught and what I see on the oscilloscope just doesn't make sense at all ...

 

[D.A.(Tony)Stewart]

Hello !

That's why I've asked why it worked in that case. How should I interpret that SH/LD and CLK have the same rising moment because they are both synchronized. I read something in the datasheet that I didn't much understand and tried to come up with the explanation, why it worked in that case (good to notify the CLK_INH in this case is always 0, author grounded this pin). So this SH/LD and CLK rising at the same time is confusing and I can't explain why it worked thus can't imagine what it interprets it as "0" or "1". It's hard to explain.

I see from the post that it's about delays but I don't see them in the video because the same rise is passed to both inputs at the same time, so the delays are the same I guess ? So D flip flop doesn't know if it's "0" or "1" so it's a hazard ? But it happened to be always "0" in this type of situation which I don't understand looking at video osciloscope and knowing that both CLK and SH/LD get the same bit from the same output which is shown in the osciloscope (or maybe they get from different output but on the osciloscope it matches).

I don't get it ...

View attachment 186417

Looking at this also confuses me because like I said both of them raises, and maybe they are delayed but I don't see it exactly (on the osciloscope of the video) and how it was achieved and how he was sure (it wasn't explained how it worked for him the author just plugged it ).
And it a bits breaks my logical thinking here because I always interpreted these type of situations as logic hazard ? Or something that give unpredictible output.

View attachment 186418

Usually in tutorials about D flip flop they don't show the situations when CLK and D are both rising at the same time, and here the SH/LD and CLK are the same type of situation.

PS.

Yes the purple/pink is imposes a yellow signal in the osciloscope (yellow is the CLK, purple is passed to SH/LD) so the yellow is not visible under purple/pink because they are I think identical ? If so where there is delay that makes both rising signals work and makes even if SH/LD is rising the D flipflop will read SH/LD as 0 and not as 0/1 because its rising.

I don't get it ...

SH/LD is async and overrides edge-triggered Clk always!

 

[Xenon02]

SH/LD is async and overrides edge-triggered Clk always!

When SH/LD is 0 then S and R are 0 so the sync part works, when SH/LD is 1 then async part works and loads the parallel data.

And here is the part where SH/LD is rising, and it is not 0 nor 1. What then ? Why it ignores CLK ?
I want to know why it ignores I can see that SH/LD can set D flip flop but it doesn't answer the question why it ignores when CLK is rising and SH/LD is also rising.

The SH/LD determines whether the data is read parallel which the parallel data is loaded asynchronic which ignores the clock, but if the SH/LD is High "1", then parallel asynchronic data is not loaded into the D flip flop but the synchronic data is loaded (the SER input), which depends on the clock.
When I don't know what happens in this rising state that it is not "1" and not "0" then how do I know if it's loading data asynchronic and ignores data like in SH/LD = 0 condition or it is getting data synchronic from D input because SH/LD = 1. I don't know and I don't know how to prove it.

Like I said I understand when SH/LD = 1 or SH/LD = 0 but I don't understand why it ignores the clock when SH/LD = rising (not 0 not 1)

EDIT:
This situation I said only shows that it could be in metastability or some state race or something similar to what I said, but in reality it is always SH/LD = rising => SH/LD = 0 somehow, but I still don't understand why.

 

[FvM]

SH/LD is async and overrides edge-triggered Clk always!

This basically answers why CLK input is ignored. The additional question is about SH/LD setup and hold time. The video refers to 74LS165, I have TI datasheet at hand.

If we read it so that "any input" th also applies to SH/LD, applying CLK edge and SH =1 simultaneously isn't guaranteed to prevent CLK action. We have a range of 0 to 10 ns delay between SH=1 and CLK edge with undefined result.

Not sure about the exact SH/LD timing in the video, didn't attempt to decode the circuit. Either there's an additional small delay or it's operating only by chance.

 

[Xenon02]

SH/LD is async and overrides edge-triggered Clk always!

This basically answers why CLK input is ignored.

For me this does not answer my question. As I explained the SH/LD determines whether D fliflop reads async from the parallel input when SH/LD = 0 or reads sync with the clock from the SER input when SH/LD = 1 so the D flip flop is when SH/LD = 0 and it is not when SH/LD = 1.
I don't understand the answer that SH/LD is always async ... When I see that when SH/LD = 1 the D flipflop is not working in async. If it worked as async then SER input wouldn't be usefull right now. The SH/LD is for enabling async or sync "mode" in D FlipFlop. So the rising edge is not 0 nor 1 so it is not simple.

Perhaps I am deadly wrong, but I still don't understand the answer.

The additional question is about SH/LD setup and hold time. The video refers to 74LS165, I have TI datasheet at hand.

If we read it so that "any input" th also applies to SH/LD, applying CLK edge and SH =1 simultaneously isn't guaranteed to prevent CLK action. We have a range of 0 to 10 ns delay between SH=1 and CLK edge with undefined result.

Not sure about the exact SH/LD timing in the video, didn't attempt to decode the circuit. Either there's an additional small delay or it's operating only by chance.

When decoding this datasheet, it says about recommending operating conditions, which was shift input setup time 20 ns and clock enable set up time which is 30 ns, so there should be 10 ns gap. This doesn't say (I guess) whether the 74LS165 is delaying it or not.

It could be that SH/LD signal is delayed because it has more logic gates than Clock, I guess. Maybe that's why it worked.
I don't know. But still it is weird.

 

[crutschow]

If all the circuits are operating from the same clock, then the signals will change after the delay of the circuit that changes the signal state.
Thus, although the signal input to the FF appears to be coincident with the clock it is actually slightly delayed.
Thus the FF input doesn't see the signal change until after the clock has already changed.
So the FF will not immediately respond to the new input, but waits until the next clock.

 

[Xenon02]

I just noticed that particular element with SH/LD has 3 different logic gates in which Clock has only 1 logic gate so there is small delay in SH/LD. So maybe that's why it worked.
Thanks

 

[D.A.(Tony)Stewart]

Unfortunately, the datasheet does not provide specifications for race between SH and CLK or between CLK INH and CLK going in opposite directions except to say ;
tsu Clock-enable setup time > 30 ns. This means you might be able to ignore CLK when synchronous with CLK INH or SH for up to a 30 ns delay.


TI had one curious spec. which does not apply with any output on this part. That is the falling edge of clock to any output, which has no effect, so it cannot be measured . Although it might affect the sync'd setup delay for CLK EN and CLK.