I2C Bus Data Timing Clarification

[Mtech1]

Hello,

I have been studying the I2C bus specification (UM10204), but I'm still unclear about the timing of data transfer and reception on the I2C bus. As far as I understand, data is transferred on the falling edge of the clock, while data is received on the rising edge of the clock.

Could you please clarify in both scenarios: when the master sends data to the slave and when the slave sends data to the master, on which clock edge does the sender send data, and on which clock edge does the receiver receive data?"

 

[FvM]

The basic point that SDA has to be stable while SCL is high. This implies that SDA has to be set by the sender before SCL rising edge, for standard speed a setup time of min. 250 ns is specified. Also SDA has to be read by the receiver latest at the falling edge, hold time is specified as zero. Below diagram illustrates the timing relation.