Our ASIC design practice is: inside the chip, MUX only. No tri-state.
External bus, tri-state if necessary.
Tri-state has problems such as timing and power consumption, as posted by another fellow. Avoid tri-state if you're doing ASIC design.
FPGA is different. FPGA devices have tri-state buffers built in. In some cases, it makes sense to use those tri-state buffers to drive long lines that are shared by blocks. This trick reduces routing congestions. However, tri-state buffers are slow, be aware of it.