Which FSM is better for designing in Verilog?

[harshaperla]

which of the fsms is faster?

Read this tutorial:
https://electrosofts.com/verilog/fsm.html
Moore is easy to design, but mealy is faster and optimized.



harshaperla

 

[manuk]

melay fsm

Colleagues, does anybody has experience with FSM generator integrated in Menthor's HDL Designer? I always write FSM manually, but would like to know your opinions. Lot of time is required to study, and it would be better first read some comments about it before.

 

[nemolee]

finite state machines melay and moore

I think we don't need to care the method we use.
If all input signal are synchronous in your design, you can use mealy mode.
For my using, I always mix these two design concepts.
For your reference.

 

[vongy]

moore, melay harel

i want to design cpu decoder,which fsm is better,why?

 

[shiv_emf]

fsm control for datapath

cpu is combination of alu n control unit !!
control unit should be accurate n it shud generate asychronous as well as asynhronous signals
hence
control unit can be designed based on Mealy n
alu is sychronous to clock ..so moore is better option !!

 

[sp3_kapil]

melay vs moor fsm

Moore over Mealy
In Mealy machine, output depends on the input. So any glitchy input will be propogated to the output. On the other hand, in more state machine output depends on the state only. So no glitches in the output.
Mealy over Moore
Moore statemachine requires one flipflop(denotes one extra state) more than Mealy. So there will always be 1 clock latency in Moore over Mealy.

So its a trade-off. You as a designer has to decide on the type of state machine to use.

 

[bobn]

fsm+data path

**broken link removed**

Some useful exercises and some methods.

Helpful to beginners

 

[manasiw2]

mealy machine used in control path

Hi all,
From implementaion point of view i read Moore are better suitable for FPGAs rather than CPLDs.Is it only because FPGAs have more flipflops than CPLDs? i would like to know the opinions about this.
Thanks in advance.