Where to start designing in ASIC?

[dev]

asic designing

where to start in asic design, I have done a projeact in vhdl in chip programming,can any one give me guidance in related field and about asic designing,links where i can find help

 

[dada1019]

asic designing

I think the vhdl coding is a starting step of asic design. You can reference the book of aisc primer for more information of that. I do not know which field you will be interested in, analog or digital, so after you read the book I recommend you will get the answer. This book can be download from this forum.

 

[dev]

Re: asic designing

I am interested in digital and i have done a project in arbiter chip degining and hope to get along in the field and know better

 

[cnspy]

asic designing

Try to find a design flow from some vendors.

 

[ymli]

asic designing

you may also google some tutorial on the web.
ex. many university courses

 

[eexuke]

Re: asic designing

**broken link removed**
You can find some ASIC building blocks introduction there. ASIC design contains countless sub-topics.Good luck!

 

[ram]

Re: asic designing

The steps fro asic designing

specification
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HDL coding
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Synthesis with (Technology library)
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STA
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place and route
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mask design sign off


ok bye

 

[soflover]

asic designing

Look here:

**broken link removed**

 

[killbuz]

Re: asic designing

hi,

ASIC design is divided into two parts. Front-end and back-end.
Front-end comprises of
a) Design -entry which can be HDL(Verilog or VHDL) or schematic.If schematic generate a netlist of it and append to your final netlist.
b) Then you synthesize the design from RTL to gates.You specify the constraints and synthesize the design according to those constraints.Then you check if the timing is met.This will be done by the synthesis tool itself, or you can use some stand alone timing analysis to do that.
c) Then you may add scan to it (for testability and controllability of the circuit after fabrication).
d) Then you generate ATPG vectors for detecting faults on chip.

Back-end
a) You do the P&R of the complete design
b) Then you do the timing analysis of post-layout netlist to make sure you have the netlist meet the timing.
c) You do physical verification and then you can generate a SPICE netlist and run SPICE on the design if you wanted.

Thanks,