Re: asic designing
hi,
ASIC design is divided into two parts. Front-end and back-end.
Front-end comprises of
a) Design -entry which can be HDL(Verilog or VHDL) or schematic.If schematic generate a netlist of it and append to your final netlist.
b) Then you synthesize the design from RTL to gates.You specify the constraints and synthesize the design according to those constraints.Then you check if the timing is met.This will be done by the synthesis tool itself, or you can use some stand alone timing analysis to do that.
c) Then you may add scan to it (for testability and controllability of the circuit after fabrication).
d) Then you generate ATPG vectors for detecting faults on chip.
Back-end
a) You do the P&R of the complete design
b) Then you do the timing analysis of post-layout netlist to make sure you have the netlist meet the timing.
c) You do physical verification and then you can generate a SPICE netlist and run SPICE on the design if you wanted.
Thanks,