what will be the output of the following code

[jesuraj]

always @(clk)
begin
a = 0;
a <= 1;
$display(a);
end

 

[ziyas]

0 1

 

[echo47]

Assuming that's Verilog, you'll just get error messages.
Missing module declaration. Undefined "clk". Undefined "a".

 

[vicky]

a=0
a=1
1 is more positive as compare to 0 and 0 is more negatie as compare to 1.
so when the 0 input output should be low when 1 out should be high.

 

[kumar_eee]

The o/p is 1 continues high (1), but there wll be glitches....