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what will be the output of the following code

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jesuraj

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always @(clk)
begin
a = 0;
a <= 1;
$display(a);
end
 

echo47

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Assuming that's Verilog, you'll just get error messages.
Missing module declaration. Undefined "clk". Undefined "a".
 

vicky

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a=0
a=1
1 is more positive as compare to 0 and 0 is more negatie as compare to 1.
so when the 0 input output should be low when 1 out should be high.
 

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