Jan 31, 2006 #1 J jesuraj Newbie level 3 Joined Jan 31, 2006 Messages 3 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,281 Activity points 1,308 always @(clk) begin a = 0; a <= 1; $display(a); end
Jan 31, 2006 #2 Z ziyas Member level 1 Joined Dec 16, 2005 Messages 39 Helped 3 Reputation 6 Reaction score 0 Trophy points 1,286 Activity points 1,696 0 1
Feb 1, 2006 #3 E echo47 Advanced Member level 6 Joined Apr 7, 2002 Messages 3,933 Helped 638 Reputation 1,274 Reaction score 90 Trophy points 1,328 Location USA Activity points 33,176 Assuming that's Verilog, you'll just get error messages. Missing module declaration. Undefined "clk". Undefined "a".
Assuming that's Verilog, you'll just get error messages. Missing module declaration. Undefined "clk". Undefined "a".
Feb 4, 2006 #4 V vicky Full Member level 4 Joined Aug 11, 2004 Messages 235 Helped 23 Reputation 46 Reaction score 4 Trophy points 1,298 Activity points 2,404 a=0 a=1 1 is more positive as compare to 0 and 0 is more negatie as compare to 1. so when the 0 input output should be low when 1 out should be high.
a=0 a=1 1 is more positive as compare to 0 and 0 is more negatie as compare to 1. so when the 0 input output should be low when 1 out should be high.
Feb 11, 2006 #5 K kumar_eee Advanced Member level 3 Joined Sep 22, 2004 Messages 814 Helped 139 Reputation 276 Reaction score 113 Trophy points 1,323 Location Bangalore,India Activity points 4,677 The o/p is 1 continues high (1), but there wll be glitches....