What will be the optimum logic circuit to implement this?

[samiran_dam]

Hi all,

I am not very knowledgeable in digital circuit. That;s why I need a bit help from you.

I have two i/p signals: i/p-1 and i/p-2 as shown in the following image. From the these two inputs I need to generate the output as also shown in the image.



Please note that the inputs are very narrow pulses. So, I have to rely on there positive edges. SR latch is not working as I have tried.

Please help.

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Hi,

A NOR gate based SR latch seems to be the working solution. When I simulate the latch in LTSpice, I am getting the intended o/p. However, in Cadence Spectre simulator the simulation throws a convergence issue. Any help?

 

[KlausST]

Hi,

This is the function of an SR latch.
I see no problem with the function itself. It will work.

But your vague information of "narrow" pulses without any waveform specification makes it impossible for us to verify the timing.

You need to define the pulses:
* low level
* rise rate
* high level
* high time
* Fall rate
* low time

And for sure we need to know the exact type of the used SR latch.

Klaus