What simulation do we have to take when design a PLL

[rficdesigner]

Hello all,

Can you please guide me which simulation I should take for each components when design a PLL (which includes PFD, Charge pump, LPF, VCO, and divider).
and PLL itself.

Thanks you.

 

[LvW]

The answer is easy: Each of the mentioned units has an input/output pair - and you have nothing to do than to simulate the input-output relationship (transfer properties).
However, in advance it is necessary to know something about the required function of each unit.

 

[rania_hassan]

Hi,
Can you clarify your question?
What 's the simulator do you use?
bets regards,
Rania

 

[rficdesigner]

I mean what simulation like DC, AC, SP ... shoud I.take for each component?
I use Cadence (spectre).
Thanks you.

 

[sunbeam]

for a circuit design, whether simple or not, tran simulation is an essential because it is the most reliable.
you should run tran simulation in each part of your pll to confirm its function and performance.

VCOss and pnoise simu to check the phase noise performance.
tran simu sweep the v-ctrl to get the vco gain and f-v curve is a must.

LPF:XF simu to check the transfer function,for LPF is simple,simu is not a must.

divider and pfd:tran simu to check the function,the largest working frequency and power.

CP:cp is a critical part. you can simu it with pfd to check the dead-zone,phase error and charge sharing.current match... I recommend you read some papers about cp.

 

[cinch]

Hi,
Before doing all these simulations, u have to first do "System-level" simulation using Matlab or Octave. With this simulation, u can fix LPF components. U have to consider the transfer function of each block and that of the full system. Check for damping ratio, Phase Margin, Bandwidth etc before fixing LPF component values.

Regards,
Cinch

 

[rficdesigner]

Thanks you all.

How about the PLL?
Currently I only run transient simulation and DC, then check whether is it locked or not.
Is it possible to check CP-PLL phase margin? Do you know how to setup simulation with Analog Design Environment - Cadence (spectre).


Regards.

 

[cinch]

Hi,
You can not do AC simulation to check for phase margin using cadence, just like u do for other circuits. For PLL, u write transfer function (TF) for each block, say
for PFD - 1/2pi
for VCO - Kvco/s (integrator)
Divider - 1/N
for LPF - 1/sC/R+1/sc etc etc.
Write down open loop TF - G(s) for the full system. Compare with the standard 2nd order or 3rd order TF. This depends on whether u have used 1st order or 2nd order loop filter. Get the equation for damping factor and ωn.
Then write closed TF - G(s)/1+G(s).H(s).
Do Matlab (or Octave) simulations for open-loop and closed loop TFs. From open-loop TF, for the required damping factor, set the value of R nad C of loop filter. Put these values in closed loop TF and findout BW and phase margin.

Only after doing this, u have to proceed for transient simulations. Thats the correct way, as far as i know.

 

[LvW]

You can not do AC simulation to check for phase margin using cadence, just like u do for other circuits.

Why not ? If you have created before a linear PLL model, you can perform an ac analysis. However, this linearized model can be applied only for the locked condition and, more than that, only for phase inputs/outputs. However, this implies no restrictions, since stability margins as PM and GM are defined only for linear systems