missbirdie
Member level 1
Hello
I need help in the following parallel to serial converter.. what's the value of load should be ?? shall it be like a clock ?? cause in all cases i tried the output is only the last bit in the shift register .. or is there something wrong with the code ???
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pts2 is
Port (clk : in STD_LOGIC;
parallel_in : in STD_LOGIC_VECTOR (7 downto 0);
load : in STD_LOGIC;
serial_out : out STD_LOGIC);
end pts2;
architecture Behavioral of pts2 is
signal reg :std_logic_vector (7 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1')then
if (load ='1') then
reg <=parallel;
else
reg<= reg (6 downto 0)&'0';
end if;
end if;
end process;
serial_out <= reg(7);
end behavioral;
Added after 3 hours 14 minutes:
I really need a very simple code.. cause i dunno how shall i assign the load signal !!!
I need help in the following parallel to serial converter.. what's the value of load should be ?? shall it be like a clock ?? cause in all cases i tried the output is only the last bit in the shift register .. or is there something wrong with the code ???
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity pts2 is
Port (clk : in STD_LOGIC;
parallel_in : in STD_LOGIC_VECTOR (7 downto 0);
load : in STD_LOGIC;
serial_out : out STD_LOGIC);
end pts2;
architecture Behavioral of pts2 is
signal reg :std_logic_vector (7 downto 0);
begin
process(clk)
begin
if (clk'event and clk='1')then
if (load ='1') then
reg <=parallel;
else
reg<= reg (6 downto 0)&'0';
end if;
end if;
end process;
serial_out <= reg(7);
end behavioral;
Added after 3 hours 14 minutes:
I really need a very simple code.. cause i dunno how shall i assign the load signal !!!