What is timing deration in reference to ASIC flow?

[pandit_vlsi]

hi all.
give me some suggestons for
1.what is timing deration?
2.where it comes into picture in ASIC FLOW?.
3.good &bad effects of it.
thanks alll
pand!t.

 

[yuenkit]

timing deration

if you only got one library, and u dont have a slower or faster library, so u try to simulate the slower or faster one by using deration

it's for Static timing analysis

 

[pandit_vlsi]

Re: timing deration

hi yuen.yes u know much about deration....
hmmmm!...
i did not get anything ....plz elaborate....
plz send some material ...
send me asap....

pandit

 

[incisive]

Re: timing deration

Hi

Is there any good book or noted for these kinda topic.

Thanks and regards
raghu

 

[coolrak]

Re: timing deration

To model the effects of PVT conditions on timing we specify the derating factor for the

chip. This derating factor is specified in the OCV analysis mode while doing STA. It

reduces the pessimism and used to model the UDSM effects of a chip for the deeper

nodes

You find relater socuments in Solvenet