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it is for convinence of chip level synthesis,
if IP provider don't provide the model, you can consider it as black box
and set timing constraint on boundary.
Thanks everyone!
One more question, if I want to synthesis a top Verilog file in which a hard macro IP is used as one of its submodules, how can I make the Eda tools---design compiler, to recognize this macro sucessfully although I can imagine it as a black box in my mind. Perhaps we need something like the standard cell library to tell the tool that this submodule should be treated as a blackbox. We call it the synthesis models of a hard macro. I mean, if I want design a hard macro for others, how can I generate such models so that others can synthesis it as a submodule? Thanks!
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