Yihan
Newbie level 6
what is the most efficient algorithm (area wise) for 16 bit/16 bit signed division for FPGA (VHDL)? Can somebody give me a couple of examples so I can compile them? I am new at programming FPGA's. Thanks.
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That's surely true, because it's just a subtractor, a shifter and a state machine. But it's slow compared to a full parallel divider.some people think the serial divider is the most efficient, is it right and why??