iamnoori
Newbie level 3
Hi.
When I create a dpram with Core generator of Xilinx,it generate all port in "std_logic_vector".but I want to drive "WEA" and "WEB" by a signal with "std_logic" type.How can I do it?
When I create a dpram with Core generator of Xilinx,it generate all port in "std_logic_vector".but I want to drive "WEA" and "WEB" by a signal with "std_logic" type.How can I do it?