what is the meaning of "std_logic_vector(0 downto 0)&qu

[iamnoori]

Hi.
When I create a dpram with Core generator of Xilinx,it generate all port in "std_logic_vector".but I want to drive "WEA" and "WEB" by a signal with "std_logic" type.How can I do it?

 

[farhada]

Re: what is the meaning of "std_logic_vector(0 downto 0

It is a silly thing that Xilinx doesn't seems to care to fix.

Just create a signal for your Xilinx_WEA and Xilinx_WEB with the same format (std_logic_vector(0 downto 0))and set the signals to something like this:


Xilinx_WEA(0) <= WEA;

And when you instantiate the IP, use the Xilinx_WEA and Xilinx_WEB there.

BR,
/Farhad