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Which nodes are connected to the outside world? It looks like the two outer bottom transistors have equal drain currents but with different Vgs values.
I got the circuit diagram just like this. However, we may suppose the output node is the M5's gate/source. So, it looks like a current source. And I think the key is the resistor R1...
it appears to be a crude cmos bandgap of the deltaVgs style. could also be used as a ptat current source with a lot less trouble.
m7 / m8 force equal currents into the two inner branches. m1 m2 act as diodes, with m2 sized to some multiple of m1 so it's vdsat is smaller - the voltage drop is made up by the resistor.
lets start from power-up, where we can assume the gates of m7/m8 are at 0, flooding the inner branches with current.
at first, the gate of m4 is higher than m3's gate so m4 pulls more current out of m5. this is mirrored out of m6 to pull the gates of m7 / m8 high and reduce the current. if the current is too low the opposite happens - m3 pulls down, allowing more current into m7/m8.
all in all, it looks pretty interesting but unless you use W/L on the order of 500/5 the matching will be bad. other problems are:
-bad power supply rejection
-tempco large compared to using regular diodes
-very affected by process variation
but for a homework question it's a good one. hope you get an A!
it appears to be a crude cmos bandgap of the deltaVgs style. could also be used as a ptat current source with a lot less trouble.
m7 / m8 force equal currents into the two inner branches. m1 m2 act as diodes, with m2 sized to some multiple of m1 so it's vdsat is smaller - the voltage drop is made up by the resistor.
lets start from power-up, where we can assume the gates of m7/m8 are at 0, flooding the inner branches with current.
at first, the gate of m4 is higher than m3's gate so m4 pulls more current out of m5. this is mirrored out of m6 to pull the gates of m7 / m8 high and reduce the current. if the current is too low the opposite happens - m3 pulls down, allowing more current into m7/m8.
all in all, it looks pretty interesting but unless you use W/L on the order of 500/5 the matching will be bad. other problems are:
-bad power supply rejection
-tempco large compared to using regular diodes
-very affected by process variation
but for a homework question it's a good one. hope you get an A!
it appears to be a crude cmos bandgap of the deltaVgs style. could also be used as a ptat current source with a lot less trouble.
m7 / m8 force equal currents into the two inner branches. m1 m2 act as diodes, with m2 sized to some multiple of m1 so it's vdsat is smaller - the voltage drop is made up by the resistor.
lets start from power-up, where we can assume the gates of m7/m8 are at 0, flooding the inner branches with current.
at first, the gate of m4 is higher than m3's gate so m4 pulls more current out of m5. this is mirrored out of m6 to pull the gates of m7 / m8 high and reduce the current. if the current is too low the opposite happens - m3 pulls down, allowing more current into m7/m8.
all in all, it looks pretty interesting but unless you use W/L on the order of 500/5 the matching will be bad. other problems are:
-bad power supply rejection
-tempco large compared to using regular diodes
-very affected by process variation
but for a homework question it's a good one. hope you get an A!
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