Well, sometimes you can and sometimes you can't. Lets use an example. Lets say you want to build a 1000 to 1020 MHz synthesizer, with 1 MHz step size. So your first try might be to use a PLL chip that divides by 1000, 1001,...1020, and use a 1 MHz phase detector comparison frequency.
But, in reading the data sheet for that particular PLL chip, you notice that there has to be a prescalar in the path, and you can chose the prescalar to divide by 8 or 16. So you set the prescalar to divide by 8. That means, right off the bat, that your oscillator is divided down to an IF frequency of 125, 125.125,...127.5 MHz. So now you need to use a phase detector comparison frequency of 125 KHz, instead of the desired 1 MHz. This lower comparison frequency causes worse phase noise, and higher spurs, since the 125 KHz clock is closer to being "inside" of the control loop bandwidth of your loop filter.
You then might search around for a better PLL chip that can count 1000, 1001,...1020 MHz without needing a prescalar, and you find one. Then you read on page 23 of the data sheet that due to some quirks of internal operation, that is can divide by 1000, 1001, 1002 but then skips a number of divisors and starts up again at divide by 1030. ( a quirk of the pulse swallowing or fractional N math).
So you might get the PLL chip you want, or have to live with less than ideal consequences.