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What is the difference between a Pre-Scaler and Divider

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Nov 23, 2005
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pre scaler main scaler

Please enlightne, in a Phase Lock Loop, what is the difference between a Pre-Scaler and Divider. When both are essentially divider architecture.

what is a prescaler

prescaler and divider are the same.
when divider used in circuit, which used for frequency prescaling, it called prescaler.

prescaler post scaler pll

The prescaler it is the first part of a high-frequency divider that divides the oscillation frequency. Usually is a D-latch circuit having minimum of parasitics to improve the maximum input frequency.
The following divider could be a standard programmable counter.

meaning of prescalar

In the old days, digital counters would not work at microwave frequencies. So you bought a prescalar divider from a microwave house, and a PLL/counter from someone like Motorola, and married the two.

Now the meaning of prescalar can still mean that, or sometimes just means
the front end divider that had a fixed divisor ratio, like divide by 8 or divide by 16, that then feeds a lower frequency variable modulus or fractional N divier chain. The prescalar chip is not seperate from the PLL chip. In this case, it is the prescalar with a fixed divide ratio that stops you from getting the narrow frequency spacing with a high phase detector reference frequency that you want to use.

frequency down scaler

Biff44, you have striked the key question which I want to ask is a PLL without the Prescaler with the Divider only, the inability to achieve the narrow frequency spacing still exist? From papers, I believe only when using a prescaler would I need to restricted the channel spacing however that does not really make sense as both are dividers topologies.

Well, sometimes you can and sometimes you can't. Lets use an example. Lets say you want to build a 1000 to 1020 MHz synthesizer, with 1 MHz step size. So your first try might be to use a PLL chip that divides by 1000, 1001,...1020, and use a 1 MHz phase detector comparison frequency.

But, in reading the data sheet for that particular PLL chip, you notice that there has to be a prescalar in the path, and you can chose the prescalar to divide by 8 or 16. So you set the prescalar to divide by 8. That means, right off the bat, that your oscillator is divided down to an IF frequency of 125, 125.125,...127.5 MHz. So now you need to use a phase detector comparison frequency of 125 KHz, instead of the desired 1 MHz. This lower comparison frequency causes worse phase noise, and higher spurs, since the 125 KHz clock is closer to being "inside" of the control loop bandwidth of your loop filter.

You then might search around for a better PLL chip that can count 1000, 1001,...1020 MHz without needing a prescalar, and you find one. Then you read on page 23 of the data sheet that due to some quirks of internal operation, that is can divide by 1000, 1001, 1002 but then skips a number of divisors and starts up again at divide by 1030. ( a quirk of the pulse swallowing or fractional N math).

So you might get the PLL chip you want, or have to live with less than ideal consequences.


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Biff44, thinking about what you have said I am still uncertain about how the Pre-scaler and divider being similar structure, one have a channel (step) limitation imposed and not the other.

Maybe I was unclear. Lets say you have two divider "components" inside of the PLL chip--a divide by 10 "prescaler" and a divide by 50 to 200 variable modulus divider.

If you were using the variable modulus divider, you could divide by 50, 51, 52....200. So if you were using a 1 MHz phase comparitor frequency, the PLL VCO output would be 50, 51,....200 MHz.

Lets say you now configure the prescalar in front of the same variable modulus divider, you could then divide by 500, 510, 520...2000. Notice it steps in units of 10 now. If you were using the same 1 MHz phase comparitor frequency, the PLL VCO output would now be 500, 510, 520...2000 MHz. (assuming the vco actually could tune this far).

So, using the prescalar typically lets you operate at a higher frequency, but with bigger step size.

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