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common clock path in a design leads to CRPR. if this occurs this adds to the skew in the design hence it needs to be removed. CRPR is a feature which can remove any common clock paths occuring in a design. this feature can be used during CTS stage.
hey CRPR is Clock Re-convergence Pessimism removal, its computing delay adjustments on the clk network ,as the name says its the removal of pessimism for the clock path .
when you set the timing analysis for BC- WC mode , the same clock path is subjected to both fast op-cond and the slow op-cond,which introduces pessimism .
A setup check at a flip-flop in a circuit ensures that the latest arriving signal at the data pin arrives before the earliest arriving signal on the clock pin. Similarly, a hold check ensures that the earliest arriving data signal arrives after the latest arriving clock signal. The earliest or latest arriving signal on the data pin of a flip-flop is usually triggered by another flip-flop.
If both the clock and the data signals share a portion of the clock network , then for common clock network , a pessimism ( maximum delay - minimum delay ) will be introduced , we need to remove the same ,also if clk source insertion delays are defined they do count.