Hi Friend,
In field of VLSI ,
the word synthesizable plays a key role.
Actually whatever design code (RTL or structural) that you write is converted into a synthesizable netlist, Where your modular approach becomes a connected gate list.
i.e. Suppose you write a RTL code for adder,
then this adder becomes a list of logically connected gate list (XOR, AND, etc ) which can be automatically implemented using tools...
Now codes that can be converted to a valid netlist for generating the hardware are said to be synthesizable..
In digital logic the concept of real numbers is not valid, for we have the logics as the two basic integers 0 and 1.
Even the IEEE standardized concepts of Strong/ weak signals donot go into the fractional or decimal point value of the number. Thats why it is not synthesizable.
Hope you are clear now.