What is symbol @ used for in Verilog?

[ASIC_intl]

@ in verilog

Is @ symbol used for timing control in verilog synthesizable? Is the @(posedge clk) a synthesizable construct?

 

[FvM]

Re: @ in verilog

If I where you, I would consult a text book or tool manual.

Synopsys HDL compiler manual e. g. is a good one. You can assume that most details apply to other synthesis tools as well.

 

[ASIC_intl]

Re: @ in verilog

Your document does not answer to my question.

Can u please refer me to the page in the document in the above link where it writes about synthesizability of @ in verilog?

 

[jbeniston]

Re: @ in verilog

Is the @(posedge clk) a synthesizable construct?

Yes, if it is of the form:

always @(posedge clk)
code

 

[dcreddy1980]

Re: @ in verilog

**broken link removed**

 

[prashanthknl]

@ in verilog

always @ () is generally used to add some elements to the sensitivity list for example

1. always @ ( posedge clk) the statement beside suggests the compiler to activate the sequence of statements under the always block usually enclosed in braces {} if the positive edge of clock is triggered or activated.
2. always @ ( data or reset or read or is_legal
or data_ready or seenTrailing or
seenZero or zeros or bits_seen ) similarly the statement beside activates the code under it if there is any change in the variables inside the always block remember the first statement changes only for positive edge or rising edge or when that signal goes from low to high.

Added after 10 minutes:

**broken link removed** try downloading the book Verilog HDL by samir palnitkar from that link and yes the always @ is synthesizable

 

[ASIC_intl]

Re: @ in verilog

But the synthesis tool always ignore the timing control events like posedge clock etc. which appear after the @ symbol.

What is the utility of @ symbol to be synthesizable if the synthesis tool ignores these events like posedge clk; (a or b or c) etc after the @ symbol ?

 

[FvM]

Re: @ in verilog

But the synthesis tool always ignore the timing control events like posedge clock.

Seems that you are using a strange synthesis tool. I wasn't aware yet of a tool of this kind.

Your document does not answer to my question.
Can u please refer me to the page in the document in the above link where it writes about synthesizability of @ in verilog?

Generally, HDL compiler is a synthesis tool. Thus any construct presented in the manual is basically synthesizable. In constrast, you won't find delay statements that are meaningful in simulation only.

You are asking very elementary HDL coding questions that are demonstrating a general lack of understanding. I think, that it wouldn't be a bad idea to read more than a few sentences answering a specific question.

 

[prashanthknl]

@ in verilog

Ignoring what does that it mean is it an error or a warning try to be specific and what's the context that you are using that @ posedge clk ???

Added after 1 minutes:

Mr ASIC_intl

 

[ASIC_intl]

Re: @ in verilog

Hi FVM

Who told you this "Thus any construct presented in the manual is basically synthesizable" ?!!!!
We have gone through many books inclucing basics.

Hi prashanthknl

If you put a # sign the synthsis tool ignores it. If you put an extra signal named extra in the sensitivity list, you will find it again synthsizes to a flop. It is due to the reason synthesis tool ignores these events like posedge clk etc after the @ symbol.

 

[FvM]

Re: @ in verilog

Who told you this "Thus any construct presented in the manual is basically synthesizable" ?!!!!

The first point is, that I know which constructs are synthesizable from practical applications rather than literature. It's always funny, if you are told, that something you're doing since long doesn't work.

The second point is, that the said Synopsys manual is informing you precisely, which Verilog constructs are supported in synthesis. Regarding events: Synchronous events (posedge, negedge) are supported, asynchronous are not supported.

 

[ASIC_intl]

Re: @ in verilog

Hi FVM!

Can u pin point to the page where it is written that @ is synthesizable clearly as you are saying?

Probably you didi not understand the constructs and it synthesizability properly. Think please and reply.

 

[FvM]

Re: @ in verilog

Discussing if @ as such is synthesisable is as meaningful as discussing this for a { } token. I already made a (negligibly simplified) statement in this regard:

Synchronous events (posedge, negedge) are supported, asynchronous are not supported.

You can find the details under always Blocks - Event Expression in the Synopsys manual.

 

[ASIC_intl]

Re: @ in verilog

HI Fvm

U have sent the manual link of synopsys. Is the verilog language reference manual different from that? I find synopsys DC manual is different from the manual whose link you have provided. Do u think that one should completely read that document which you have sent to work in Digital design?

 

[FvM]

Re: @ in verilog

Unfortunately I don't know the Synopsys DC manual. Regarding the HDL compiler manual, that's identical in part to documents provided for Xilinx XST, as far as I've seen, I think it's really instructive. That's why it's used e.g. for stanford classes, I guess. Normally, you would consult specific chapters rather than reading it in total.

It was helpful to me in understanding some Verilog concepts, as I'm mostly using VHDL for FPGA design, but Verilog only on customer request or with existing IP. The other important document is the Verilog IEEE specification, it also contains some synthesis relevant language elements that are omitted in the Synopsys manual, if I remember right. But it hasn't the purpose to tell what's synthesisable in hardware, cause it is covering Verilog code for simulation as well.

 

[ASIC_intl]

Re: @ in verilog

HI FvM

Do u have requirement for VLSI engineers in your company now? how many years of experience are u looking at?

 

[FvM]

Re: @ in verilog

Personally, I'm working as a consultant without employees, thus I don't have requirements. Good luck!

 

[ASIC_intl]

Re: @ in verilog

Hi FvM

Do your company has any requiremnet?

Added after 1 hours 30 minutes:

what is the company u work in?

 

[ASIC_intl]

Re: @ in verilog

Hi FVM

Do u think that to write RTL one should first know what the synthesizable constructs are?

If is not so, should one designer understand from intution the synthesizability of the code he is writing?

 

[FvM]

Re: @ in verilog

Do u think that to write RTL one should first know what the synthesizable constructs are?

I think, it's important to understand the basic concepts of synchronous logic, how a design is translated to gates and flip-flops. From this knowledge, you almost see how a RTL is mapped to logic resources. Some details are specific for logic families, e. g. if flip-flops have additional asynchronous inputs or a reset only and can't be known in any case.

It seems to me, that the said concepts are more easy to understand for a designer, who has experience with hardware logic design.