What is \***SEQGEN***\ in synthesis of netlist using Design Compiler?

[ASIC_intl]

Hi

I got some \**SEQGEN**\ while doing synthesis using design compiler.

What is this \**SEQGEN** \ ?

Please let me know in detail.

Regards

 

[ljxpjpjljx]

Re: synthesis of netlist

I think it is some keyword in DC ,you can consult the manual in DC!

 

[atena]

Re: synthesis of netlist

Hi

I got some \**SEQGEN**\ while doing synthesis using design compiler.

What is this \**SEQGEN** \ ?

Please let me know in detail.

Regards

This \**SEQGEN**\ elements appear when you forget to amp your design with link library ... Give the proper Link and Target Libraries and after "Analyze" and "Elaborate" you have to issue "Link" and "Compile" commands ... After that those SEQGEN will be removed ...

 

[ASIC_intl]

Re: synthesis of netlist

Hi

The link_library command was used and then link and compile commands were used.

Regards