Kind of bringing up a topic from the dead, but something like this would be very useful. Ideally, you spec out your particular design's constraints in Chisel and Chisel will dump some config file (or something into the Verilog code) that will make sure that everything is interpreted correctly by the desired tool.Hello,
I found (*S = "TRUE"*) in verilog code.
What does it mean??
the pic is below.
Please help me!
this code is part of True Random Number Generator!