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What is (*S = "TRUE") in Verilog?

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Min02

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Hello,
I found (*S = "TRUE"*) in verilog code.
What does it mean??
the pic is below.
Please help me!
this code is part of True Random Number Generator!
 

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This is an Attribute , which is like an embedded note attached to the source text. They were introduced in Verilog-2001 to replace ad-hoc comment pragmas so they could formally parsed and processed by other applications. See section 5.12 Attributes in the IEEE 1800-2017 SystemVerilog LRM.

Most attributes are used by synthesis tools to direct how the source code is to be implemented. I haven't seen this one before so you'll probably have to ask the person/vendor who wrote the code.
 

Hello,
I found (*S = "TRUE"*) in verilog code.
What does it mean??
the pic is below.
Please help me!
this code is part of True Random Number Generator!
Kind of bringing up a topic from the dead, but something like this would be very useful. Ideally, you spec out your particular design's constraints in Chisel and Chisel will dump some config file (or something into the Verilog code) that will make sure that everything is interpreted correctly by the desired tool.

I had an issue where the Verilog synthesized properly (passed simulation) only when distributed RAM was inferred, but the timing didn't match what was supported by BRAM (which was inferred by default), so I had to add in the additional synthesis option.
 

As stated, Verilog attributes are tool specific. You need to consult the respective tool manual. I never came across a single letter attribute name like "S", usually attributes have descriptive names.
 

this looks a lot like a typical keep/preserve attribute, but like others, I have not seen this S before. has to be specific to a tool. is this code automatically generated by any chance?
 

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