zorro said:In a digital circuit, the hold time is the minimum time that an input signal must remain stable after the active edge of the clock in order to assure that that input is correctly recognized.
If a circuit has a negative hold time, this means that the input can change before the clock edge and nevertheless the old level will be correctly recognized. This can be produced by internal delay of the clock signal. For example, if a D flip flop has a hold time of –1ns, the level present at the D input up to 1 ns before the clock edge is the level captured, provided it was stable up to that moment.
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synq said:Is there any physical chip available (CMOS) with negative inbuild holdtime??
Is there Negative Set up time? Never Heard of it..
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What about the sum of Set up and Hold time? Whether it should be 0,<0,>0 or based on the requirement.
Can anybody elaborate the neg set up time..
I have read in few articles that the set up time will be always positive.
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