what is negative holdtime??????

[synq]

negative hold time

Iam haunted with negative slack....

again

negative holdtime....again negative setup time..

can anyone help me to figure out what is the significance on negative holdtime..

pros and cons???

where should i dig more info on it...

 

[zorro]

hold time negative

Hi synq

In a digital circuit, the hold time is the minimum time that an input signal must remain stable after the active edge of the clock in order to assure that that input is correctly recognized.
If a circuit has a negative hold time, this means that the input can change before the clock edge and nevertheless the old level will be correctly recognized. This can be produced by internal delay of the clock signal. For example, if a D flip flop has a hold time of –1ns, the level present at the D input up to 1 ns before the clock edge is the level captured, provided it was stable up to that moment.

Setup time is the minimum time that an input must stabilize to its logical level before the active edge of the clock in order to assure that that input is correctly recognized.
If a circuit has a negative setup time, this means that the input can change after the clock edge and nevertheless the new level will be correctly recognized. This can be produced by internal delay of the clock signal. For example, if a D flip flop has a setup time of –1ns, the level present at the D input from 1 ns after the clock edge is the level captured, provided it remains stable from that moment.

I hope this helps
Regards

Z

 

[Ace-X]

negative setup time

In a digital circuit, the hold time is the minimum time that an input signal must remain stable after the active edge of the clock in order to assure that that input is correctly recognized.
If a circuit has a negative hold time, this means that the input can change before the clock edge and nevertheless the old level will be correctly recognized. This can be produced by internal delay of the clock signal. For example, if a D flip flop has a hold time of –1ns, the level present at the D input up to 1 ns before the clock edge is the level captured, provided it was stable up to that moment.
......

Bravo, zorro! Really nice and clear explanation! :sm28:
There is only one mistype: the red-colored text should be changed to "This can be produced by internal delay of the data input".


Ace-X.

 

[zorro]

negative hold time

Thank you, Ace-X. I made a mistake.
Now the symmetry between hold and setup times is complete.
I hope it is clear after your correction.
Regards

Z

 

[xworld2008]

negative holdtime

see this

 

[synq]

negative hold

thanks zorro and acex ..now the problem here is..

how come a synopsys DC compiler fails to synthesis all because we had a negative slack in the timing report it generated. Do that means circuit cannot hold a negative holdtime or the timing model lacks the negative timing discription..?? Is there any limitations??

i could see..if i try to say the negative slack time is given with a particular intention to allow the input change even after for a few more time before the clock edge happens...am i getting gods of timing theory angry here....

Is there any physical chip available (CMOS) with negative inbuild holdtime??

 

[srisrisri]

what is meaning of negative setup and hold time

hi
there are some flops with negative set up . they are called as hybrid flip-flop(if i correctly remember!). it internally has an edge detection circuit and delay and then a flip flop. the delayed edge is fed to the internal flop and hence we get -ve set up. but i have not come across them in any of the standard libraries such as TSMC 0.18. so i think it is completely dependant on the vendor of the technology. and also i have some doubt regarding the tools that we are having presently. i don't know whether the tools such as DC take advantage the -ve set-up flops even if we have them in the target library.
anybody who has worked with the libraries with -ve set-up flops and the tools that support them can explain more.
srisrisri

 

[srisrisri]

why hold time negative

hi
there are some flops with negative set up . they are called as hybrid flip-flop(if i correctly remember!). it internally has an edge detection circuit and delay and then a flip flop. the delayed edge is fed to the internal flop and hence we get -ve set up. but i have not come across them in any of the standard libraries such as TSMC 0.18. so i think it is completely dependant on the vendor of the technology. and also i have some doubt regarding the tools that we are having presently. i don't know whether the tools such as DC take advantage of the -ve set-up flops even if we have them in the target library.
anybody who has worked with the libraries with -ve set-up flops and the tools that support them can explain more.
srisrisri

 

[zorro]

negative hold time

Is there any physical chip available (CMOS) with negative inbuild holdtime??

This is an example From Motorola FACT Data:

74AC74 hold time:
typ @ Ta=25°C: -2.0 ns @ 3.3Vcc; -1.5 ns @ 5.0Vcc
guaranteed: 0.5 ns

Z

 

[synq]

hold time negative wiki

Thanks zorro..


Sri sri sri wrote....

>>>i don't know whether the tools such as DC take advantage of the -ve set-up flops even if we have them in the target library. >>>

But why big guns like Synopsys and Cadence fear to give such values in the standard cell library..any clues?

I have come across synthesis script quiting on negative time slacks..

 

[funzero]

when will hold time be begative

i have read an article , it give an new point.
when input signal is measured , it will use 90% of VDD for logic 1,and 10% for logic 10. but when we come to output signal it often use 50% VDD for 1 and 0 boundary .
In some cases , the input signal does not run to 90% level VDD , but signal has changed to 50%, will produce a negtive timing parameter .

 

[bendrift]

synthesis for negative hold time

good article

 

[realbinbin]

negative setup time hold time

it is really depend on the device

 

[dhawalkadao]

negative set up time

This is a good article

 

[ved9876]

how to implement negative hold time

Negative setup times are achieved by pulse triggered latches. the latch design will in way that when internal clock is fed to it, it will convert it an pulse clock, by means of a circuitary. Draw a pulse clock and you will come to know.

 

[navateja]

Hi.
I have a query here. Isn't the concept of negative setup time same as that of hold time??

 

[yadavvlsi]

Re: negative hold time

Setup time is the minimum amount of time data must be stable at input before arriving the active edge of the clock.
That is to say, if a flip-flop defines a 200 ps data setup time,then the data must arrive 200 ps before active edge of clock arrives.

Hold time is the minimum amount of time data must be stable at input after arriving the active edge of the clock.
i.e both setup and hold times are measured w.r.t the active egde of clock.

For a Pure flop(containing no extra gates) setup and hold time always will be a positive number. Now, A flop can be a part of a bigger component.These components are available as a part of stranded cell library. Setup and hold time can be negative depending on where you measure the setup and hold time, if you measure setup and hold time at component level. These can be negative also.

Consider that a flop is sitting inside a component.

Given:

T_dataflop is the arrival time of data at the flop.
T_clkflop is the arrival time of clock edge at the flop.
T_flopsetup is the setup time of pure flop.

Therefore:

Equation 1: T_dataflop < = T_clkflop - T_flopsetup

That is to say.. "Data must arrive at the flop T_flopsetup(setup time) before the clock edge arrives". For example, say T_clkflop is 10 ns and T_flopsetup is 200 ps. In this case, T_dataflop must be less than 9.8 ns in order to meet setup timing.

With that in mind, let's factor component level timing:

T_datacomp is the arrival time of the data at the component pin.
T_clkcomp is the arrival time of the clock edge at the component pin.
T_datadelay is the delay of the data from the component pin to the embedded flop.
T_clkdelay is the delay of the clock from the component pin to the embedded flop.


By these definitions, we can say:

T_datacomp + T_datadelay = T_dataflop
T_clkcomp + T_clkdelay = T_clkflop



Therefore, substituting into Equation 1 from above,

Equation 2: T_datacomp + T_datadelay < = (T_clkcomp + T_clkdelay) - T_flopsetup


For illustration, assume that the following values were characterized (during product testing):

T_datadelay = 700 ps
T_clkdelay = 800 ps
T_flopsetup = 200 ps

Equation 2 becomes:
T_datacomp + 700 ps < = T_clkcomp + 800 ps - 200 ps
T_datacomp + 700 ps < = T_clkcomp + 600 ps
T_datacomp < = T_clkcomp - 100 ps

This implies a component level setup time of 100 ps.( Remember setup time pure flop is 200 ps)


Now assume that T_datadelay = 500 ps, and substitute into Eq 2:
T_datacomp + 500 ps < = T_clkcomp + 800 ns - 200 ps
T_datacomp + 500 ps < = T_clkcomp + 600 ps
T_datacomp <= T_clkcomp + 100 ps

This means that the data must arrive at the component 100 ps after the clock and thus we have a negative setup time.

Same way hold time also can be negative. Consider case: If add a buffer in front of flop which has delay greater than hold time of flop and measure the hold time at the input of buffer instead of FF then this become negative hold time with respect to the active edge of the clock. If this buffer is a part of FF then the hold time will negative.


There are many components available in stranded cell library that embed a flop inside. These components will be a part of our design. Static Timing Analysis(STA) tool check setup time violation at a component by finding the Slack
Slack=Required arrival time of data-Actual arrival time of data. This must be positive number. This means data must reach at required time or before to met setup.

For reg 2 reg path:
Required arrival time= Total period of clock - Setup time
Actual arrival time= Tclock>q+Tcomb. delay

So the value of setup and hold time is used by STA tool to calculate timing..

 

[chiragh.wild]

Re: negative hold time

Hi yadav..thanks for your post..this thread solved most of my issues with setup-hold time.

I had one basic doubt though,

The setup and hold timing information for the data pin depends on two indexes ..
index_1("0.4, 0.57, 0.84"); /* Data transition */
index_2("0.4, 0.57, 0.84"); /* Clock transition */

Thus, with a D pin rise transition time of 0.4ns and CLK pin rise transition time of 0.84ns, some value is chosen from the LUT..

I did'nt understand how setup and hold time depends upon these two transition times..?? Can you explain giving some values as examples???

 

[Prashanthanilm]

Re: negative hold time

Is there Negative Set up time? Never Heard of it..

- - - Updated - - -

What about the sum of Set up and Hold time? Whether it should be 0,<0,>0 or based on the requirement.

Can anybody elaborate the neg set up time..
I have read in few articles that the set up time will be always positive.

 

[rakesh.patro1988]

Re: negative hold time

The sum of setup and hole time should be positive. the main purpose is that data should arrive at time and slack is positive. both setup and hold can not be negative at the same time.

Is there Negative Set up time? Never Heard of it..

- - - Updated - - -

What about the sum of Set up and Hold time? Whether it should be 0,<0,>0 or based on the requirement.

Can anybody elaborate the neg set up time..
I have read in few articles that the set up time will be always positive.