What is meant by 90nm.12um - a CMOS question

[santuvlsi]

CMOS question?

Dear Dudes,

We say as 90nm .13um

actually what is meant by this,

also when an IC is getting Fabricated on 90nm will it be of same length or above or below.

Santu

 

[master_picengineer]

CMOS question?

These are the process technology. For exemple 90 nm tech means that the Transistors channel is realy 90 nm length.

 

[santuvlsi]

Re: CMOS question?

Dear master piece engineer,

But i was told as it will be/ it has to be little more than that.

suppose if 90nm means we will be working on 1um.

sometimes double how far is this true and what is the actual thing?

also i was told during fabrication it may go down ie from 1um and will be some where near 90+nm . so that during fabrication it can be alterd or brought to 90nm fabrication .

but if fab starts excatly 90nm then due to fab error it will come down below 90nm

which cannot be extended.


What is the real fact in this regard?


Santu

 

[onlymusic16]

Re: CMOS question?

here the concept of leff (effective length) would come into picture.

 

[amitjagtap]

CMOS question?

santuVLSI
whatever you heard is true. For 90 nm techecnology
chip is always fabricated using 90nm + to get fisible result and to keep some margin for the error caused bye lithography process.

 

[salma ali bakr]

Re: CMOS question?

there are always margins of errors taken into account...so that when any effects occur during fabrication processes, the yield doesn't decrease in any way!

 

[mhowell67]

Re: CMOS question?

In the case of 90nm, or any process, wouldn't that be the size of the smallest possible gate length? Isn't it likely that a design or standard cell library would have many gates that are larger than the minimum? I honestly don't know - most of my background is analog using bicmos processes.

 

[muralicrl]

Re: CMOS question?

Hi,

Whatever you are mentioning is obviously true. It is the process technology accuracy parameter. Less than that the process technology doesn't support.
I think I am clear.

If you need more details, contact me.

Regards,

N.Muralidhara

 

[praveenvaliki]

Re: CMOS question?

it actually resembles the channel length in a MOSFET
as it reduces many process parameters are effected
maximum technology cannot be less than the inter atomic distance of the element used

 

[kansal]

Re: CMOS question?

if we are using 90 nm technology,it means minimum length of channel is 90nm.but it is always recommended to use length more then this..

 

[lordsathish]

Re: CMOS question?

Hi everyone...
Doesn the 90nm also correspond to the minimum distance between two interconnects....?

 

[master_picengineer]

Re: CMOS question?

Hi everyone...
Doesn the 90nm also correspond to the minimum distance between two interconnects....?

There is no relation.

 

[steshenko]

CMOS question?

And you have delay in interconnections - in 0?18 main delay in gates

 

[AdvaRes]

Re: CMOS question?

Hi everyone...
Doesn the 90nm also correspond to the minimum distance between two interconnects....?

There is no relation.

What is the average distance between interconnects for each technology. Is there a relation with the gate length ?

 

[forkschgrad]

Re: CMOS question?

Hi everyone...
Doesn the 90nm also correspond to the minimum distance between two interconnects....?

There is no relation.

What is the average distance between interconnects for each technology. Is there a relation with the gate length ?

no relation. it's the interconnect length that has a relation to gate length to prevent antenna effect.

 

[xstal]

Re: CMOS question?

130, 90, 60, 45 nm are technology nodes. It does of course mean the channel length of the transistor. But to say that, in a given technology, e.g. 90 nm, channel length varies from 70 to 100 nm from vendor to vendor and that is what makes one product better than the other in a given technology node. These technology nodes basically come from moores law...
Wondering how?!?!?!?!?!
well, when a technology scales down, it follows moores law, i.e. doubling the number of transistors in a given area. We bisect the square along its diagonal to fit two transistors that was earlier accomodating one transistor. So the technology node scales down by a factor of square root of 2.
I hope you can make further calculations to see what is 90, 60. etc....