what is HFN syntheisis in CTS?

[vamsi_addagada]

what is hfn synthesis

plz any one explain what is HFN syntheisis in CTS?

 

[raju3295]

hfn on astro

Generally HFN is done for the nets which have more no fanouts like clk pins .reset pins and scan enables,,, generalyy we consider them as ideal while doing the synthesis, while doing the placement these will be buffered up to meet the drc values except the clk pins and at the CTS stage clk n/w is buffered such a way to attain the intended skew and latency values,,

PLEASE SOME ONE CAN CORRECT ME IF AM IN THE WRONG PATH

 

[vlsitechnology]

如何对reset做hfn astro

This is not for Clock pins...This is only for reset and scan enable signals.....
Reply me

 

[pythonlong]

hfn synthesis

HFN constains three type:
1.clock
2.reset
3.general purpose

solution:
1.set_ideal_network (-no_propagate) or set_dont_touch_network
2.set high_fanout_net_threshold,high_fanout_net_pin_capacitance

when use dc,then insert buffer wen APR use Astro or Encounter

a paper of SNUG

 

[raju3295]

HI VLSI
YES your right it is not for clock pins,,, but my view was while synthesis we consider the clk n/w as also ideal along with HFN and in placement we buffer rest of the HFN excluding the clk n/w and in CTS we do the synthesis for clock pins,,,so in this point of view, clk pins are also can be considered as HFN , but these are synthesiszed later in the implementation.

PLEASE DO COMMENT ON MY VIEW

 

[vlsitechnology]

According to my knowledge HFN is completely different phenomena.....How clock pins can be considered as HFN?...Yaar logic synthesis is different and clock tree synthesis is different..the same question was asked in our intstitute also...HFN is done for High fanout nets such as reset, scan enable....

I donno about synthesis i did not worked on Synthesis but i know this is something different wt ur thinking...ask someone else and let me know....

Reply me

 

[raju3295]

Hi Vlsi
can u tell me wht u will be doing while HFN,,,its only buffering na,,, and its the same with Clock pins also ... i accept logic synthesis and HFN ,CTS are totally diffrent,, as u do the same buffering with HFN and with the CTS , why cant the clock pins can't be called as HFN.. i agree that the target for CTS is different when compare with the syntheis of resets like pins

 

[pythonlong]

clock is diferent from other HFN.

latency,transition,uncertainty can effect chip

 

[santuvlsi]

HFN is done for other than clock net like reset nets,scan enables and some high fanout nets.

we need to HFN , actually we set a number , means more than this number treated as High fan out net .otherwise the high fanout net will see a lot of load and this net will c a large laod capacitance hence huge delays.

CTS is also similar to HFN but the difference is CTS includes in meeting constraints like latency skew to meet timings

hope u understood

 

[raju3295]

hi sant
thanks for adding some more information to the discussion.......... as a conclusion we can say that CTS is a special case of HFN synthesis where the implmentation has to consider more constraints ,and by default the CLK nets are considered as HFN.
IS am with you