What is common use file format for I/O pads in ASIC flow ?

[elektor]

asic i/o pads

Hi,
I think about something similar like for example UCF in FPGA xilinx.

Mainly I'm focus on forward-backward annotation with information about IO Pads placement in ASIC flow. Maybe someone has some materials or information about this topic ?

What format has SOC Encounter for this information ? Maybe someone can provide here several rows ?

 

[azerm]

i/o asic pad

Hi,

PAD insertion in ASIC is very differenent with FPGA. There is no good way for automatic pad insertion, instead designer may put each PAD in the top level netlist same as other blocks.

Also other PAD issues like power & ground, multi_supply pads, ESD rules, filler and breaker and ... must be consdered.

 

[elektor]

Re: What is common use file format for I/O pads in ASIC flow

Hi,

PAD insertion in ASIC is very differenent with FPGA. There is no good way for automatic pad insertion, instead designer may put each PAD in the top level netlist same as other blocks.

Also other PAD issues like power & ground, multi_supply pads, ESD rules, filler and breaker and ... must be consdered.

Of course I've understood that it is very different. But for example Silicon Ensemble had *.ioc file with IO Pads location.

Regarding of other PAD issues... Have you got any materials about these rules.
For example: how many power & ground pads I need and where place them ?

 

[jtonfat]

Re: What is common use file format for I/O pads in ASIC flow

I would really appreciate to know this too!. I'm learning the Cadence design flow from RTL to GDSII and I'm trapped with this. I'm being looking the cadence manuals but i didn't find anything.