Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
As u see FIFO are used maily in clock croosing domains,
According to me , TWo stag FIFO indicates that there must two set of FIFO in design so that we can obtain the needed time doimain to make the circuit work corectly.
But the depth of those FIFO can be designed according to need.
But we can increase the depth of first FIFO then we don't need the second FIFO?
Can anyone explain the reason behind not increasing the depth of the first FIFO, and adding an extra FIFO for the same?
To understand few thoughts towards
the Depth of FIFO,
how to decide on the Depth of the FIFO
At what scenario the Depth of the FIFO will be questionable or need more thougts,
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
