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What is a two-stage FIFO?

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dear dude,

As u see FIFO are used maily in clock croosing domains,

According to me , TWo stag FIFO indicates that there must two set of FIFO in design so that we can obtain the needed time doimain to make the circuit work corectly.

But the depth of those FIFO can be designed according to need.

Hope i am right


But we can increase the depth of first FIFO then we don't need the second FIFO?
Can anyone explain the reason behind not increasing the depth of the first FIFO, and adding an extra FIFO for the same?

Fifo depth two might mean it should hold data of 2 it could be bytes or packets like ethernet etc

Dear Designer,

my 2 cents in the discussion..

To understand few thoughts towards
the Depth of FIFO,
how to decide on the Depth of the FIFO
At what scenario the Depth of the FIFO will be questionable or need more thougts,

please do visit,

Praise the Lord

best regards,
[learn ASIC Chip design for Free]

This is usually a pipeline decoupling FIFO... used more to seperate domains and seperate acknowledge signals rather than as a bus

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