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when u do inplace optimization and clock tree sythesis . core utilization will increase by buffer placement.
also u can have advantage if u have free space interms thermal effect.
but u have pay price for it
Can you suggest what is the maximum limit is to Total utilisation.
I mean which design one prefers a Standard design having 85% utilisation or a design having 95% utilisation.
Thanks uin advance
It is recommended that the utilization be 75% for a good routing.
Added after 6 minutes:
However, you could do it as the case may be. If you have less interconnect, the utilization should be larger, vice versa. I think you could achieve an appropriate utilization after a few times of repeat.