What is a good core utilization percent ?

[liujingshu]

Core utilization

Hi, guy
My chip's core utilization only 81%. Does it meaning very bad?

 

[pandit_vlsi]

Re: Core utilization

hi ..
i dont think your design is bad.
i have seen many designs with utilisation b/w 50-65% also.how come your's is bad
...
pandit

 

[aravind]

Core utilization

when u do inplace optimization and clock tree sythesis . core utilization will increase by buffer placement.
also u can have advantage if u have free space interms thermal effect.
but u have pay price for it

 

[eexuke]

Re: Core utilization

Hi, guy
My chip's core utilization only 81%. Does it meaning very bad?

81% utilization is pretty high...

 

[zyphor]

Re: Core utilization

pretty good design, of course you should address die size, if die size is small ,the utilization should be high.

 

[jjww110]

Core utilization

normaly, if you have some bus,the utilization should be acceptable!!

 

[semi_jl]

Core utilization

81% is very good, I think. However, you may improve it if you can.

 

[abhi_123]

Core utilization

Hey Guys,
Can you suggest what is the maximum limit is to Total utilisation.
I mean which design one prefers a Standard design having 85% utilisation or a design having 95% utilisation.
Thanks uin advance

 

[darylz]

Core utilization

not bad i think.

 

[semi_jl]

Core utilization

It is recommended that the utilization be 75% for a good routing.

Added after 6 minutes:

However, you could do it as the case may be. If you have less interconnect, the utilization should be larger, vice versa. I think you could achieve an appropriate utilization after a few times of repeat.