#### fahim1

##### Member level 4

i have the following code,that i use component inside it.but have the same errors and warnings for each line of component,i dont understand the errors.

Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 library ieee; use IEEE.STD_LOGIC_1164.ALL; --use ieee.std_logic_arith.all; --package needed for signed --use IEEE.NUMERIC_STD.all; use IEEE.std_logic_unsigned.all; ----------------------------------------- entity firserial is --generic (n :integer :=4; --number of coefficients --m :integer :=4); --number of bits represent coefficients port( x : in std_logic_vector (3 downto 0); clk,rst : in std_logic; y : out std_logic_vector (7 downto 0)); end firserial; ------------------------------------ architecture firserial_arch of firserial is -------------------------------------- component serialnew2 is port(a,b : in std_logic_vector(3 downto 0); clk : in std_logic; out3 : out std_logic_vector(7 downto 0)); end component; --------------------------------------- type registers is array (2 downto 0) of std_logic_vector(3 downto 0); type coefficients is array (3 downto 0) of std_logic_vector(3 downto 0); signal reg : registers := ("0000","0000","0000"); constant coef : coefficients := ("0001","0010","0011","0100"); ----------------------------------- -------------------------------- begin process(clk,rst) variable acc,prod : std_logic_vector (7 downto 0) := (others => '0'); variable a,b,c : std_logic_vector(7 downto 0) := (others => '0') ; begin -----------------reset-------------------- if rst='1' then for i in 2 downto 0 loop for j in 3 downto 0 loop reg(i)(j) <= '0'; end loop; end loop; -------------register inference + MAC ----------- elsif (clk'event and clk='1') then acc := (others => '0'); --acc := coef(0)*x ; ok --prod := coef(1)*reg(2)+coef(2)*reg(1)+coef(3)*reg(0); u1 : serialnew2 port map (coef(0), x,clk , acc); u2 : serialnew2 port map (coef(1), reg(2),clk , a); u3 : serialnew2 port map (coef(2), reg(1), clk, b); u4 : serialnew2 port map (coef(3), reg(0), clk, c); prod := a+ b+ c ; acc := acc + prod ; reg <= x & reg(2 downto 1 ); end if; y <= acc; end process; end firserial_arch;