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10533 VHDL wait statement error

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Newbie level 6
Nov 28, 2015
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I am a new with VHDL coding and I have some issues with the wait statement with quartus. With Vivado it works fine no problems with the compilation. First of all is "wait for 1 ns; " synthesizable ?
I am trying to compile the design and it fails as predeclared. Then I found and example from the internet and it fails again in the wait statement and then an error occurs.

Error (10533): VHDL Wait Statement error at half_adder.vhd (27): Wait Statement must contain condition clause with UNTIL keyword

First off a wait for 1 ns won't synthesize to any logic, so no it's not actually synthesizable (I beleive Xilinx ignores it compelely, which is probably why it works).

You other question doesn't show the code (half_adder.vhd) causing the Error (10533) you are seeing, so we can only guess what you wrote that is causing a problem.

FYI, A good rule to follow is to avoid WAIT statements in synthesizable code. This is especially true if you are using it to delay signals to move them off the clock edges so simulation is "easier' to look at.

Anything that can be synthesized using a WAIT statement is easily coded in one of the standard templates that can be easily found and are usually in the coding style guides that the FPGA vendors publish.

I used this code for experiment, it has almost the same structure.

    procedure xor_delay(
        signal a_in    : in  std_ulogic;
        signal b_in   : in  std_ulogic;
        signal sum  : out std_ulogic) is
        wait for 2 ns;
        sum <= a_in xor b_in;
    end procedure;

So it would be easier if I move the delay on the clock edges, I suppose as a process and not as a procedure with wait until (clk = '1')?

You had right about Xilinx, it ignores the delay statement.
ignoring unsynthesizable construct: wait statement with no conditon

Now in Xilinx fails to synthesize the project, just because I moved the wait statement under the sum <= a_in xor b_in;. The problem is with Xilinx that I don't understand where is the problem. How I suppose to find the problem in my code?

Too many positional options when parsing 'Projects/CarryLookaheadAdder/CarryLookaheadAdder.srcs/utils_1/imports/synth_1/carry_lookahead_adder.dcp', please type 'read_checkpoint -help' for usage info.

I solved the all the problems with Xilinx, but I don't understand, why the file can be compiled directly with Modelsim using exactly the above implementation without an error but in the synthesis will not work?

FPGA hardware has no means to implement timed wait or delay statements, thus they are not synthesizable.

Modelsim is a code simulator, and will simulate exactly what you write. There is a lot of code that is not synthesisable but is perfectly valid and useful for simulation. Like wait statements.

Vhdl was originally created as a modeling language. It was later that tools were created to convert the code to circuits. But only a subset of the language is supported.

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