signal s0: STD_LOGIC_VECTOR (31 downto 0):= (others => '0'); signal s1: STD_LOGIC_VECTOR (31 downto 0):= (others => '0');
signal s2: STD_LOGIC_VECTOR (31 downto 0):= (others => '0'); signal s3: STD_LOGIC_VECTOR (31 downto 0):= (others => '0');
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signal s50: STD_LOGIC_VECTOR (31 downto 0):= (others => '0'); signal s51: STD_LOGIC_VECTOR (31 downto 0):= (others => '0');
signal s52: STD_LOGIC_VECTOR (31 downto 0):= (others => '0'); signal s53: STD_LOGIC_VECTOR (31 downto 0);
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map20: Delay port map(clk,reset,s12,s20);
map21: R_shifter port map(s20,s21);
map22: Adder port map(s12,s21,s22);
map23: L_shifter port map(s34,s23);
map24: Adder port map(s19,s23,s24);
map25: Delay port map(clk,reset,s52,s25);
map26: Delay port map(clk,reset,s25,s26);
map27: Delay port map(clk,reset,s26,s27);
map28: Delay port map(clk,reset,s27,s28);
map29: R_shifter port map(s28,s29);
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