What causes WARNING:Xst:2677 in a VHDL code?

[Twix25]

Hello,

I have got a warning in implementation of my vhdl code but I didn't find the problem cause

warning msg:

WARNING:Xst:2677 - Node <map28/out_del_3> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <map28/out_del_2> of sequential type is unconnected in block <top>.
WARNING:Xst:2677 - Node <map28/s_delay_3> of sequential type is unconnected in block <top>.

delay code

entity Delay is
    Port ( clk : in  STD_LOGIC;
	        reset: in STD_LOGIC;
           in_del : in  STD_LOGIC_VECTOR (31 downto 0);
           out_del : out  STD_LOGIC_VECTOR (31 downto 0));
			  
end Delay;

architecture Behavioral of Delay is

signal s_delay: STD_LOGIC_VECTOR (31 downto 0);

begin

process (clk)
  
  
  begin
   if clk='1' and clk'event  then
       
		 if reset='0'  then
    	   out_del <= s_delay;
   		s_delay <= in_del;
        else
		   out_del <= "00000000000000000000000000000000";
		 end if; 
  end if; 
  
 
 end process;                                

end Behavioral;

\]

 

[shanmugaveld]

xst:2677

I guess one of ur instantiation output is not properly mapped.

 

[Twix25]

sequential type is unconnected

Thks for reply.
I check the mapping and all seems correct: Here is an extract from my mapping code top level:

signal s0: STD_LOGIC_VECTOR (31 downto 0):= (others => '0');    signal s1: STD_LOGIC_VECTOR (31 downto 0):= (others => '0'); 
signal s2: STD_LOGIC_VECTOR (31 downto 0):= (others => '0');    signal s3: STD_LOGIC_VECTOR (31 downto 0):= (others => '0'); 
                 . 
                 .
signal s50: STD_LOGIC_VECTOR (31 downto 0):= (others => '0');   signal s51: STD_LOGIC_VECTOR (31 downto 0):= (others => '0');
signal s52: STD_LOGIC_VECTOR (31 downto 0):= (others => '0');   signal s53: STD_LOGIC_VECTOR (31 downto 0);

                .
                .
                .
map20: Delay port map(clk,reset,s12,s20);
map21: R_shifter port map(s20,s21);
map22: Adder port map(s12,s21,s22);
map23: L_shifter port map(s34,s23);
map24:  Adder port map(s19,s23,s24);
map25: Delay port map(clk,reset,s52,s25);
map26: Delay port map(clk,reset,s25,s26);
map27: Delay port map(clk,reset,s26,s27);
map28: Delay port map(clk,reset,s27,s28);
map29: R_shifter port map(s28,s29);
                .
                .

All problems is comming with the delay sub bloc.

 

[shanmugaveld]

of sequential type is unconnected in block

It seems to be proper only...
usually this warning will occur only when the signals bits are not used..
it seems that s_delay_3, out_del_2 & out_del_3 are not used in the design...
whether the signals are taken out from the top module?
if the functionality of ur design works fine in gate level simulation u can ignore these warnings.