Jan 21, 2014 #1 S shaiko Advanced Member level 5 Joined Aug 20, 2011 Messages 2,644 Helped 303 Reputation 608 Reaction score 297 Trophy points 1,363 Activity points 18,302 Code: signal x : std_logic_vector ( 31 downto 0 ) ; signal y : std_logic_vector ( 31 downto 0 ) ; signal nibble: std_logic_vector ( 2 downto 0 ) ; nibble <= x ( 30 downto 28 ) ; y <= ( 30 downto 28 => nibble , others => 'Z' ) ; -- compilation fails on this line The above code fails compilation with the following error: "Expression does not match type std_ulogic" Why?
Code: signal x : std_logic_vector ( 31 downto 0 ) ; signal y : std_logic_vector ( 31 downto 0 ) ; signal nibble: std_logic_vector ( 2 downto 0 ) ; nibble <= x ( 30 downto 28 ) ; y <= ( 30 downto 28 => nibble , others => 'Z' ) ; -- compilation fails on this line The above code fails compilation with the following error: "Expression does not match type std_ulogic" Why?
Jan 21, 2014 #2 A axcdd Full Member level 3 Joined Jan 29, 2012 Messages 154 Helped 58 Reputation 116 Reaction score 57 Trophy points 1,308 Activity points 2,133 Vectors aggregate is only possible in vhdl 2008. In ealier versions u can aggregate only bits. so Code: y <= ( 30 => nibble(2) , 29 => nibble(1), 28 => nibble(0), others => 'Z' ) ;
Vectors aggregate is only possible in vhdl 2008. In ealier versions u can aggregate only bits. so Code: y <= ( 30 => nibble(2) , 29 => nibble(1), 28 => nibble(0), others => 'Z' ) ;
Jan 21, 2014 #3 T TrickyDicky Advanced Member level 7 Joined Jun 7, 2010 Messages 7,110 Helped 2,081 Reputation 4,181 Reaction score 2,048 Trophy points 1,393 Activity points 39,769 or instead write: y(30 downto 28) <= nibble; y(31) <= 'Z'; y(27 downto 0) <= (others => 'Z');
Jan 21, 2014 #4 A axcdd Full Member level 3 Joined Jan 29, 2012 Messages 154 Helped 58 Reputation 116 Reaction score 57 Trophy points 1,308 Activity points 2,133 By the way is there any free vhdl enviroment that support vhdl 2008 with PSL commands ?. I know about AHDL and Questa but both are quite expensive
By the way is there any free vhdl enviroment that support vhdl 2008 with PSL commands ?. I know about AHDL and Questa but both are quite expensive